/openbmc/qemu/target/sparc/ |
H A D | win_helper.c | 29 dst[0] = src[0]; in memcpy32() 56 target_ulong icc = 0; in cpu_get_psr() 58 icc |= ((int32_t)env->cc_N < 0) << PSR_NEG_SHIFT; in cpu_get_psr() 59 icc |= ((int32_t)env->cc_V < 0) << PSR_OVF_SHIFT; in cpu_get_psr() 60 icc |= ((int32_t)env->icc_Z == 0) << PSR_ZERO_SHIFT; in cpu_get_psr() 69 (env->psref ? PSR_EF : 0) | in cpu_get_psr() 71 (env->psrs ? PSR_S : 0) | in cpu_get_psr() 72 (env->psrps ? PSR_PS : 0) | in cpu_get_psr() 73 (env->psret ? PSR_ET : 0) | env->cwp; in cpu_get_psr() 83 env->cc_N = deposit64(env->cc_N, 0, 32, -(val & PSR_NEG)); in cpu_put_psr_icc() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/media/ |
H A D | qcom,sdm660-camss.yaml | 109 port@0: 341 iommus = <&mmss_smmu 0xc00>, 342 <&mmss_smmu 0xc01>, 343 <&mmss_smmu 0xc02>, 344 <&mmss_smmu 0xc03>; 349 reg = <0x0ca00020 0x10>, 350 <0x0ca30000 0x100>, 351 <0x0ca30400 0x100>, 352 <0x0ca30800 0x100>, 353 <0x0ca30c00 0x100>, [all …]
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H A D | qcom,sm8250-camss.yaml | 113 port@0: 308 reg = <0 0xac6a000 0 0x2000>, 309 <0 0xac6c000 0 0x2000>, 310 <0 0xac6e000 0 0x1000>, 311 <0 0xac70000 0 0x1000>, 312 <0 0xac72000 0 0x1000>, 313 <0 0xac74000 0 0x1000>, 314 <0 0xacb4000 0 0xd000>, 315 <0 0xacc3000 0 0xd000>, 316 <0 0xacd9000 0 0x2200>, [all …]
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/openbmc/u-boot/arch/riscv/include/asm/ |
H A D | encoding.h | 16 #define MSTATUS_UIE 0x00000001 17 #define MSTATUS_SIE 0x00000002 18 #define MSTATUS_HIE 0x00000004 19 #define MSTATUS_MIE 0x00000008 20 #define MSTATUS_UPIE 0x00000010 21 #define MSTATUS_SPIE 0x00000020 22 #define MSTATUS_HPIE 0x00000040 23 #define MSTATUS_MPIE 0x00000080 24 #define MSTATUS_SPP 0x00000100 25 #define MSTATUS_HPP 0x00000600 [all …]
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/openbmc/linux/drivers/mfd/ |
H A D | wm5110-tables.c | 22 { 0x80, 0x3 }, 23 { 0x44, 0x20 }, 24 { 0x45, 0x40 }, 25 { 0x46, 0x60 }, 26 { 0x47, 0x80 }, 27 { 0x48, 0xa0 }, 28 { 0x51, 0x13 }, 29 { 0x52, 0x33 }, 30 { 0x53, 0x53 }, 31 { 0x54, 0x73 }, [all …]
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H A D | cs47l90-tables.c | 18 { 0x8A, 0x5555 }, 19 { 0x8A, 0xAAAA }, 20 { 0x4CF, 0x0700 }, 21 { 0x171, 0x0003 }, 22 { 0x101, 0x0444 }, 23 { 0x159, 0x0002 }, 24 { 0x120, 0x0444 }, 25 { 0x1D1, 0x0004 }, 26 { 0x1E0, 0xC084 }, 27 { 0x159, 0x0000 }, [all …]
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H A D | cs47l85-tables.c | 18 { 0x80, 0x0003 }, 19 { 0x213, 0x03E4 }, 20 { 0x177, 0x0281 }, 21 { 0x197, 0x0281 }, 22 { 0x1B7, 0x0281 }, 23 { 0x4B1, 0x010A }, 24 { 0x4CF, 0x0933 }, 25 { 0x36C, 0x011B }, 26 { 0x4B8, 0x1120 }, 27 { 0x4A0, 0x3280 }, [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
H A D | oss_2_4_d.h | 27 #define mmIH_VMID_0_LUT 0xe00 28 #define mmIH_VMID_1_LUT 0xe01 29 #define mmIH_VMID_2_LUT 0xe02 30 #define mmIH_VMID_3_LUT 0xe03 31 #define mmIH_VMID_4_LUT 0xe04 32 #define mmIH_VMID_5_LUT 0xe05 33 #define mmIH_VMID_6_LUT 0xe06 34 #define mmIH_VMID_7_LUT 0xe07 35 #define mmIH_VMID_8_LUT 0xe08 36 #define mmIH_VMID_9_LUT 0xe09 [all …]
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H A D | oss_3_0_1_d.h | 27 #define mmIH_VMID_0_LUT 0xe00 28 #define mmIH_VMID_1_LUT 0xe01 29 #define mmIH_VMID_2_LUT 0xe02 30 #define mmIH_VMID_3_LUT 0xe03 31 #define mmIH_VMID_4_LUT 0xe04 32 #define mmIH_VMID_5_LUT 0xe05 33 #define mmIH_VMID_6_LUT 0xe06 34 #define mmIH_VMID_7_LUT 0xe07 35 #define mmIH_VMID_8_LUT 0xe08 36 #define mmIH_VMID_9_LUT 0xe09 [all …]
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H A D | oss_2_0_d.h | 27 #define mmIH_VMID_0_LUT 0xf50 28 #define mmIH_VMID_1_LUT 0xf51 29 #define mmIH_VMID_2_LUT 0xf52 30 #define mmIH_VMID_3_LUT 0xf53 31 #define mmIH_VMID_4_LUT 0xf54 32 #define mmIH_VMID_5_LUT 0xf55 33 #define mmIH_VMID_6_LUT 0xf56 34 #define mmIH_VMID_7_LUT 0xf57 35 #define mmIH_VMID_8_LUT 0xf58 36 #define mmIH_VMID_9_LUT 0xf59 [all …]
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H A D | oss_3_0_d.h | 27 #define mmIH_VMID_0_LUT 0xe00 28 #define mmIH_VMID_1_LUT 0xe01 29 #define mmIH_VMID_2_LUT 0xe02 30 #define mmIH_VMID_3_LUT 0xe03 31 #define mmIH_VMID_4_LUT 0xe04 32 #define mmIH_VMID_5_LUT 0xe05 33 #define mmIH_VMID_6_LUT 0xe06 34 #define mmIH_VMID_7_LUT 0xe07 35 #define mmIH_VMID_8_LUT 0xe08 36 #define mmIH_VMID_9_LUT 0xe09 [all …]
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/openbmc/linux/arch/riscv/include/asm/ |
H A D | csr.h | 13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ 15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ 17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ 19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 22 #define SR_FS_OFF _AC(0x00000000, UL) 23 #define SR_FS_INITIAL _AC(0x00002000, UL) [all …]
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/openbmc/linux/tools/lib/perf/ |
H A D | mmap.c | 25 refcount_set(&map->refcnt, 0); in perf_mmap__init() 38 map->prev = 0; in perf_mmap__mmap() 41 MAP_SHARED, fd, 0); in perf_mmap__mmap() 49 return 0; in perf_mmap__mmap() 58 refcount_set(&map->refcnt, 0); in perf_mmap__munmap() 71 BUG_ON(map->base && refcount_read(&map->refcnt) == 0); in perf_mmap__put() 120 return 0; in overwrite_rb_find_range() 125 if (pheader->size == 0) { in overwrite_rb_find_range() 128 return 0; in overwrite_rb_find_range() 172 return 0; in __perf_mmap__read_init() [all …]
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/openbmc/linux/drivers/slimbus/ |
H A D | stream.c | 19 * @segdist_code: Segment Distribution Code SD[11:0] 20 * @seg_offset_mask: Segment offset mask in SD[11:0] 30 {1, 1536, 0x200, 0xdff}, 31 {2, 768, 0x100, 0xcff}, 32 {4, 384, 0x080, 0xc7f}, 33 {8, 192, 0x040, 0xc3f}, 34 {16, 96, 0x020, 0xc1f}, 35 {32, 48, 0x010, 0xc0f}, 36 {64, 24, 0x008, 0xc07}, 37 {128, 12, 0x004, 0xc03}, [all …]
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/openbmc/qemu/target/m68k/ |
H A D | cpu.h | 28 #define OS_BYTE 0 54 #define EXCP_TRAP0 32 /* User trap #0. */ 68 #define EXCP_RTE 0x100 69 #define EXCP_SEMIHOSTING 0x101 71 #define M68K_DTTR0 0 101 uint32_t cc_x; /* always 0/1 */ 104 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 105 uint32_t cc_z; /* == 0 or unused */ 227 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 233 #define CCF_C 0x01 [all …]
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/openbmc/qemu/target/riscv/ |
H A D | cpu_bits.h | 13 #define EXT_STATUS_MASK 0x3ULL 17 #define FSR_RD (0x7 << FSR_RD_SHIFT) 20 #define FPEXC_NX 0x01 21 #define FPEXC_UF 0x02 22 #define FPEXC_OF 0x04 23 #define FPEXC_DZ 0x08 24 #define FPEXC_NV 0x10 27 #define FSR_AEXC_SHIFT 0 38 #define CSR_SSP 0x011 41 #define CSR_USTATUS 0x000 [all …]
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/openbmc/linux/arch/x86/pci/ |
H A D | irq.c | 25 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) 26 #define PIRQ_VERSION 0x0100 28 #define IRT_SIGNATURE (('$' << 0) + ('I' << 8) + ('R' << 16) + ('T' << 24)) 39 * Never use: 0, 1, 2 (timer, keyboard, and cascade) 43 unsigned int pcibios_irq_mask = 0xfff8; 46 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000, 47 0, 0, 0, 0, 1000, 100000, 100000, 100000 87 sum = 0; in pirq_check_routing_table() 88 for (i = 0; i < rt->size; i++) in pirq_check_routing_table() 91 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%lx\n", in pirq_check_routing_table() [all …]
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/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | sdm630.dtsi | 33 #clock-cells = <0>; 40 #clock-cells = <0>; 48 #size-cells = <0>; 53 reg = <0x0 0x100>; 73 reg = <0x0 0x101>; 88 reg = <0x0 0x102>; 103 reg = <0x0 0x103>; 115 CPU4: cpu@0 { 118 reg = <0x0 0x0>; 138 reg = <0x0 0x1>; [all …]
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H A D | sc8180x.dtsi | 27 #clock-cells = <0>; 33 #clock-cells = <0>; 41 #size-cells = <0>; 43 CPU0: cpu@0 { 46 reg = <0x0 0x0>; 50 qcom,freq-domain = <&cpufreq_hw 0>; 57 clocks = <&cpufreq_hw 0>; 75 reg = <0x0 0x100>; 79 qcom,freq-domain = <&cpufreq_hw 0>; 86 clocks = <&cpufreq_hw 0>; [all …]
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H A D | sm8250.dtsi | 81 #clock-cells = <0>; 89 #clock-cells = <0>; 95 #size-cells = <0>; 97 CPU0: cpu@0 { 100 reg = <0x0 0x0>; 101 clocks = <&cpufreq_hw 0>; 108 qcom,freq-domain = <&cpufreq_hw 0>; 110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 116 cache-size = <0x20000>; 122 cache-size = <0x400000>; [all …]
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/openbmc/linux/include/linux/mfd/madera/ |
H A D | registers.h | 14 #define MADERA_SOFTWARE_RESET 0x00 15 #define MADERA_HARDWARE_REVISION 0x01 16 #define MADERA_CTRL_IF_CFG_1 0x08 17 #define MADERA_CTRL_IF_CFG_2 0x09 18 #define MADERA_CTRL_IF_CFG_3 0x0A 19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16 20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17 21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18 22 #define MADERA_TONE_GENERATOR_1 0x20 23 #define MADERA_TONE_GENERATOR_2 0x21 [all …]
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/openbmc/linux/sound/soc/codecs/ |
H A D | wm5100.h | 26 #define WM5100_CLKSRC_MCLK1 0 34 #define WM5100_CLKSRC_ASYNCCLK 0x100 39 #define WM5100_FLL_SRC_MCLK1 0x0 40 #define WM5100_FLL_SRC_MCLK2 0x1 41 #define WM5100_FLL_SRC_FLL1 0x4 42 #define WM5100_FLL_SRC_FLL2 0x5 43 #define WM5100_FLL_SRC_AIF1BCLK 0x8 44 #define WM5100_FLL_SRC_AIF2BCLK 0x9 45 #define WM5100_FLL_SRC_AIF3BCLK 0xa 50 #define WM5100_SOFTWARE_RESET 0x00 [all …]
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/openbmc/linux/drivers/hwmon/ |
H A D | nct6775-core.c | 22 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3 23 * nct6116d 9 5 5 3+3 0xd280 0xc1 0x5ca3 24 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3 25 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3 26 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3 27 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3 28 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3 29 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3 30 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3 31 * nct6796d 14 7 7 2+6 0xd420 0xc1 0x5ca3 [all …]
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/openbmc/qemu/disas/ |
H A D | riscv.c | 31 /* 0 is reserved for rv_op_illegal. */ 1019 "0x1p+0", "min", "0x1p-16", "0x1p-15", 1020 "0x1p-8", "0x1p-7", "0x1p-4", "0x1p-3", 1021 "0x1p-2", "0x1.4p-2", "0x1.8p-2", "0x1.cp-2", 1022 "0x1p-1", "0x1.4p-1", "0x1.8p-1", "0x1.cp-1", 1023 "0x1p+0", "0x1.4p+0", "0x1.8p+0", "0x1.cp+0", 1024 "0x1p+1", "0x1.4p+1", "0x1.8p+1", "0x1p+2", 1025 "0x1p+3", "0x1p+4", "0x1p+7", "0x1p+8", 1026 "0x1p+15", "0x1p+16", "inf", "nan" 1259 { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, [all …]
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/openbmc/linux/drivers/pci/ |
H A D | quirks.c | 81 * Return 0 if the link has been successfully retrained. Return an error 87 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ in pcie_failed_link_retrain() 265 u8 cls = 0; in pci_apply_final_quirks() 299 return 0; in pci_apply_final_quirks() 337 pci_read_config_byte(d, 0x82, &dlc); in quirk_passive_release() 341 pci_write_config_byte(d, 0x82, dlc); in quirk_passive_release() 387 pci_read_config_dword(dev, 0x40, &pmbase); in quirk_tigerpoint_bm_sts() 388 pmbase = pmbase & 0xff80; in quirk_tigerpoint_bm_sts() 391 if (pm1a & 0x10) { in quirk_tigerpoint_bm_sts() 393 outw(0x10, pmbase); in quirk_tigerpoint_bm_sts() [all …]
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