Searched +full:0 +full:x92400000 (Results 1 – 7 of 7) sorted by relevance
155 reg = <0x596e8000 0x88000>;165 mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;171 reg = <0x92400000 0x1000000>;175 reg = <0x942f0000 0x8000>;179 reg = <0x942f8000 0x8000>;184 reg = <0x94300000 0x100000>;190 reg = <0x3b6e8000 0x88000>;199 mboxes = <&mu2 0 0>,200 <&mu2 1 0>,201 <&mu2 3 0>;
37 reg = <0x00000000 0x80000000 0 0x40000000>;48 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M452 decoder_boot: decoder_boot@0x84000000 {54 reg = <0 0x84000000 0 0x2000000>;56 encoder_boot: encoder_boot@0x86000000 {58 reg = <0 0x86000000 0 0x2000000>;60 rpmsg_reserved: rpmsg@0x90000000 {62 reg = <0 0x90000000 0 0x400000>;64 decoder_rpc: decoder_rpc@0x90400000 {66 reg = <0 0x90400000 0 0x1000000>;[all …]
35 #size-cells = <0>;38 A35_0: cpu@0 {41 reg = <0x0 0x0>;52 reg = <0x0 0x1>;87 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */88 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */100 reg = <0 0x92400000 0 0x2000000>;120 mboxes = <&lsio_mu1 0 0121 &lsio_mu1 1 0152 reg = <0x2c4 6>;[all …]
55 #size-cells = <0>;58 A35_0: cpu@0 {61 reg = <0x0 0x0>;63 i-cache-size = <0x8000>;66 d-cache-size = <0x8000>;78 reg = <0x0 0x1>;80 i-cache-size = <0x8000>;83 d-cache-size = <0x8000>;95 reg = <0x0 0x2>;97 i-cache-size = <0x8000>;[all …]
17 pinctrl-0 = <&pinctrl_gpio_bkl_on>;18 brightness-levels = <0 45 63 88 119 158 203 255>;28 pinctrl-0 = <&pinctrl_gpio8>;30 gpio-fan,speed-map = < 0 082 pinctrl-0 = <&pinctrl_wifi_pdn>;93 pinctrl-0 = <&pinctrl_gpio7>;105 pinctrl-0 = <&pinctrl_usbh_en>;135 reg = <0 0x84000000 0 0x2000000>;140 reg = <0 0x86000000 0 0x200000>;145 reg = <0 0x86200000 0 0x200000>;[all …]
48 #size-cells = <0>;50 A53_0: cpu@0 {53 reg = <0x0>;57 i-cache-size = <0x8000>;60 d-cache-size = <0x8000>;73 reg = <0x1>;77 i-cache-size = <0x8000>;80 d-cache-size = <0x8000>;91 reg = <0x2>;95 i-cache-size = <0x8000>;[all …]
17 #clock-cells = <0>;21 pinctrl-0 = <&divclk1_default>;26 #clock-cells = <0>;31 pinctrl-0 = <&divclk4_pin_a>;59 pinctrl-0 = <&irled_default>;64 reg = <0x0 0x88800000 0x0 0x1400000>;68 /* This platform has all PIL regions offset by 0x1400000 */71 reg = <0x0 0x89c00000 0x0 0x6200000>;77 reg = <0x0 0x8fe00000 0x0 0x1b00000>;83 reg = <0x0 0x91900000 0x0 0xa00000>;[all …]