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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dxgene-pci-msi.txt8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Dopenbmc-flash-layout-128.dtsi8 u-boot@0 {
9 reg = <0x0 0xe0000>; // 896KB
14 reg = <0xe0000 0x20000>; // 128KB
19 reg = <0x100000 0x900000>; // 9MB
24 reg = <0xa00000 0x5600000>; // 86MB
29 reg = <0x6000000 0x2000000>; // 32MB
H A Dopenbmc-flash-layout-64.dtsi11 u-boot@0 {
12 reg = <0x0 0xe0000>; // 896KB
17 reg = <0xe0000 0x20000>; // 128KB
22 reg = <0x100000 0x900000>; // 9MB
27 reg = <0xa00000 0x2000000>; // 32MB
32 reg = <0x2a00000 0x1600000>; // 22MB
H A Dopenbmc-flash-layout-64-alt.dtsi11 u-boot@0 {
12 reg = <0x0 0xe0000>; // 896KB
17 reg = <0xe0000 0x20000>; // 128KB
22 reg = <0x100000 0x900000>; // 9MB
27 reg = <0xa00000 0x2000000>; // 32MB
32 reg = <0x2a00000 0x1600000>; // 22MB
/openbmc/qemu/linux-user/arm/
H A Dtarget_syscall.h7 /* uregs[0..15] are r0 to r15; uregs[16] is CPSR; uregs[17] is ORIG_r0 */
12 #define ARM_SYSCALL_BASE 0x900000
13 #define ARM_THUMB_SYSCALL 0
15 #define ARM_NR_BASE 0xf0000
H A Dcpu_loop.c114 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
122 oldval = tswap32(env->regs[0]); in arm_kernel_cmpxchg32_helper()
138 env->regs[0] = cpsr ? 0 : -1; in arm_kernel_cmpxchg32_helper()
149 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
161 addr = env->regs[0]; in arm_kernel_cmpxchg64_helper()
197 cpsr = 0; in arm_kernel_cmpxchg64_helper()
204 env->regs[0] = cpsr ? 0 : -1; in arm_kernel_cmpxchg64_helper()
220 case 0xffff0fa0: /* __kernel_memory_barrier */ in do_kernel_trap()
223 case 0xffff0fc0: /* __kernel_cmpxchg */ in do_kernel_trap()
226 case 0xffff0fe0: /* __kernel_get_tls */ in do_kernel_trap()
[all …]
/openbmc/linux/arch/arm/include/uapi/asm/
H A Dunistd.h17 #define __NR_OABI_SYSCALL_BASE 0x900000
18 #define __NR_SYSCALL_MASK 0x0fffff
21 #define __NR_SYSCALL_BASE 0
33 #define __ARM_NR_BASE (__NR_SYSCALL_BASE+0x0f0000)
/openbmc/qemu/linux-headers/asm-arm/
H A Dunistd.h17 #define __NR_OABI_SYSCALL_BASE 0x900000
20 #define __NR_SYSCALL_BASE 0
33 #define __ARM_NR_BASE (__NR_SYSCALL_BASE+0x0f0000)
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-msm8660.yaml47 reg = <0x900000 0x4000>;
H A Dqcom,gcc-other.yaml41 reg = <0x900000 0x4000>;
/openbmc/u-boot/include/configs/
H A Dls1043a_common.h38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
67 #define CONFIG_SPL_TEXT_BASE 0x10000000
68 #define CONFIG_SPL_MAX_SIZE 0x17000
69 #define CONFIG_SPL_STACK 0x1001e000
70 #define CONFIG_SPL_PAD_TO 0x1d000
74 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
75 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
[all …]
H A Dls1046a_common.h38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
66 #define CONFIG_SPL_TEXT_BASE 0x10000000
67 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
68 #define CONFIG_SPL_STACK 0x10020000
69 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
70 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
71 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
[all …]
/openbmc/linux/arch/arm/boot/dts/gemini/
H A Dgemini-ssi1328.dts17 memory@0 {
20 reg = <0x00000000 0x8000000>;
28 bootargs = "console=ttyS0,19200n8 initrd=0x900000,9M";
37 #size-cells = <0>;
54 ethernet-port@0 {
67 reg = <0x30000000 0x03200000>;
70 pinctrl-0 = <&pflash_default_pins>;
75 /* Eraseblock at 0xfe0000 */
76 fis-index-block = <0x7F>;
82 pinctrl-0 = <&gpio0_default_pins>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-am654-serdes.yaml56 - description: Clock output names for SERDES 0
86 reg = <0x900000 0x2000>;
96 mux-controls = <&serdes_mux 0>;
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-linksys-cobra.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
H A Darmada-385-linksys-caiman.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
H A Darmada-385-linksys-shelby.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dpm9g45.dts19 reg = <0x70000000 0x8000000>;
40 pinctrl_nand_rb: nand-rb-0 {
55 timer@0 {
57 reg = <0>, <1>;
67 pinctrl-0 = <
73 slot@0 {
74 reg = <0>;
91 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
95 reg = <0x3 0x0 0x800000>;
108 at91bootstrap@0 {
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D204.out5 wrote 134217728/134217728 bytes at offset 0
8 wrote 115343360/115343360 bytes at offset 0
32 0/1048576 bytes allocated at offset 127 MiB
33 110 MiB (0x6e00000) bytes allocated at offset 0 bytes (0x0)
34 18 MiB (0x1200000) bytes not allocated at offset 110 MiB (0x6e00000)
37 read 1000/1000 bytes at offset 0
58 0 0x800000 TEST_DIR/t.IMGFMT
59 0x900000 0x2400000 TEST_DIR/t.IMGFMT
60 0x3c00000 0x1100000 TEST_DIR/t.IMGFMT
61 0x6a00000 0x400000 TEST_DIR/t.IMGFMT
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm6115-tlmm.yaml65 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
107 reg = <0x500000 0x400000>,
108 <0x900000 0x400000>,
109 <0xd00000 0x400000>;
116 gpio-ranges = <&tlmm 0 0 114>;
/openbmc/qemu/tests/tcg/arm/
H A Dhello-arm.c1 #define __NR_SYSCALL_BASE 0x900000
15 } while (0)
22 "mov %0,r0" \
33 "mov %0,r0" \
47 "mov\t%0,r0" \
63 "mov\t%0,r0" \
80 "mov\t%0,r0" \
98 "mov\t%0,r0" \
112 exit1(0); in _start()
/openbmc/u-boot/doc/uImage.FIT/
H A Dhowto.txt89 Image 0 (kernel)
96 Load Address: 0x00000000
97 Entry Point: 0x00000000
103 Configuration 0 (config-1)
123 Load address: 0x900000
133 Image 0 (kernel)
137 Data Start: 0x009000e0
141 Load Address: 0x00000000
142 Entry Point: 0x00000000
148 Configuration 0 (config-1)
[all …]
/openbmc/linux/sound/drivers/vx/
H A Dvx_cmd.c19 [CMD_VERSION] = { 0x010000, 2, RMH_SSIZE_FIXED, 1 },
20 [CMD_SUPPORTED] = { 0x020000, 1, RMH_SSIZE_FIXED, 2 },
21 [CMD_TEST_IT] = { 0x040000, 1, RMH_SSIZE_FIXED, 1 },
22 [CMD_SEND_IRQA] = { 0x070001, 1, RMH_SSIZE_FIXED, 0 },
23 [CMD_IBL] = { 0x080000, 1, RMH_SSIZE_FIXED, 4 },
24 [CMD_ASYNC] = { 0x0A0000, 1, RMH_SSIZE_ARG, 0 },
25 [CMD_RES_PIPE] = { 0x400000, 1, RMH_SSIZE_FIXED, 0 },
26 [CMD_FREE_PIPE] = { 0x410000, 1, RMH_SSIZE_FIXED, 0 },
27 [CMD_CONF_PIPE] = { 0x42A101, 2, RMH_SSIZE_FIXED, 0 },
28 [CMD_ABORT_CONF_PIPE] = { 0x42A100, 2, RMH_SSIZE_FIXED, 0 },
[all …]
/openbmc/qemu/include/hw/arm/
H A Draspi_platform.h67 #define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
68 #define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
69 #define INTE_OFFSET 0x2000 /* VC Interrupt controller */
70 #define ST_OFFSET 0x3000 /* System Timer */
71 #define TXP_OFFSET 0x4000 /* Transposer */
72 #define JPEG_OFFSET 0x5000
73 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
74 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
75 #define ARBA_OFFSET 0x9000
76 #define BRDG_OFFSET 0xa000 /* RPiVid ASB for BCM2838 (BCM2711) */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dconfig.h13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
25 #define CONFIG_SYS_PAGE_SIZE 0x10000
31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
32 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
48 #define GICD_BASE 0x06000000
49 #define GICR_BASE 0x06100000
52 #define SMMU_BASE 0x05000000 /* GR0 Base */
69 #define CCI_MN_BASE 0x04000000
[all …]

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