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/openbmc/qemu/tests/multiboot/
H A Dmmap.out10 0x0 - 0x9fc00: type 1 [entry size: 20]
11 0x9fc00 - 0xa0000: type 2 [entry size: 20]
12 0xf0000 - 0x100000: type 2 [entry size: 20]
13 0x100000 - 0x7fe0000: type 1 [entry size: 20]
14 0x7fe0000 - 0x8000000: type 2 [entry size: 20]
15 0xfffc0000 - 0x100000000: type 2 [entry size: 20]
17 mmap start: 0x9000
18 mmap end: 0x9090
19 real mmap end: 0x9090
28 0x0 - 0x9fc00: type 1 [entry size: 20]
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8544ds.dts16 reg = <0 0 0 0>; // Filled by U-Boot
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
26 ranges = <0x0 0x0 0xe0000000 0x100000>;
30 reg = <0 0xe0008000 0 0x1000>;
31 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
37 /* IDSEL 0x11 J17 Slot 1 */
38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
[all …]
H A Dmpc8568mds.dts22 reg = <0x0 0x0 0x0 0x0>;
26 reg = <0x0 0xe0005000 0x0 0x1000>;
27 ranges = <0x0 0x0 0xfe000000 0x02000000
28 0x1 0x0 0xf8000000 0x00008000
29 0x2 0x0 0xf0000000 0x04000000
30 0x4 0x0 0xf8008000 0x00008000
31 0x5 0x0 0xf8010000 0x00008000>;
33 nor@0,0 {
37 reg = <0x0 0x0 0x02000000>;
42 bcsr@1,0 {
[all …]
H A Dmpc8572ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
56 reg = <0x03e00000 0x00200000>;
62 reg = <0x04000000 0x00400000>;
67 reg = <0x04400000 0x03b00000>;
72 reg = <0x07f00000 0x00060000>;
77 reg = <0x07f60000 0x00020000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dralink,rt3883-pci.txt38 address. The value must be 0. As such, 'interrupt-map' nodes do not
53 address. The value must be 0.
105 reg = <0x10140000 0x20000>;
114 #address-cells = <0>;
128 bus-range = <0 255>;
130 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
131 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
134 interrupt-map-mask = <0xf800 0 0 7>;
137 0x8800 0 0 1 &pciintc 18
138 0x8800 0 0 2 &pciintc 18
[all …]
/openbmc/linux/sound/soc/codecs/
H A Drt274.h14 #define RT274_AUDIO_FUNCTION_GROUP 0x01
15 #define RT274_DAC_OUT0 0x02
16 #define RT274_DAC_OUT1 0x03
17 #define RT274_ADC_IN2 0x08
18 #define RT274_ADC_IN1 0x09
19 #define RT274_DIG_CVT 0x0a
20 #define RT274_DMIC1 0x12
21 #define RT274_DMIC2 0x13
22 #define RT274_MIC 0x19
23 #define RT274_LINE1 0x1a
[all …]
H A Drt286.h14 #define RT286_AUDIO_FUNCTION_GROUP 0x01
15 #define RT286_DAC_OUT1 0x02
16 #define RT286_DAC_OUT2 0x03
17 #define RT286_ADC_IN1 0x09
18 #define RT286_ADC_IN2 0x08
19 #define RT286_MIXER_IN 0x0b
20 #define RT286_MIXER_OUT1 0x0c
21 #define RT286_MIXER_OUT2 0x0d
22 #define RT286_DMIC1 0x12
23 #define RT286_DMIC2 0x13
[all …]
H A Drt298.h14 #define RT298_AUDIO_FUNCTION_GROUP 0x01
15 #define RT298_DAC_OUT1 0x02
16 #define RT298_DAC_OUT2 0x03
17 #define RT298_DIG_CVT 0x06
18 #define RT298_ADC_IN1 0x09
19 #define RT298_ADC_IN2 0x08
20 #define RT298_MIXER_IN 0x0b
21 #define RT298_MIXER_OUT1 0x0c
22 #define RT298_MIXER_OUT2 0x0d
23 #define RT298_DMIC1 0x12
[all …]
/openbmc/qemu/tests/qtest/
H A Dam53c974-test.c21 qtest_outl(s, 0xcf8, 0x80001004); in test_cmdfifo_underflow_ok()
22 qtest_outw(s, 0xcfc, 0x01); in test_cmdfifo_underflow_ok()
23 qtest_outl(s, 0xcf8, 0x8000100e); in test_cmdfifo_underflow_ok()
24 qtest_outl(s, 0xcfc, 0x8a000000); in test_cmdfifo_underflow_ok()
25 qtest_outl(s, 0x8a09, 0x42000000); in test_cmdfifo_underflow_ok()
26 qtest_outl(s, 0x8a0d, 0x00); in test_cmdfifo_underflow_ok()
27 qtest_outl(s, 0x8a0b, 0x1000); in test_cmdfifo_underflow_ok()
37 qtest_outl(s, 0xcf8, 0x80001010); in test_cmdfifo_underflow2_ok()
38 qtest_outl(s, 0xcfc, 0xc000); in test_cmdfifo_underflow2_ok()
39 qtest_outl(s, 0xcf8, 0x80001004); in test_cmdfifo_underflow2_ok()
[all …]
/openbmc/linux/include/linux/
H A Dscx200.h13 #define scx200_cb_present() (scx200_cb_base!=0)
16 #define SCx200_DOCCS_BASE 0x78 /* DOCCS Base Address Register */
17 #define SCx200_DOCCS_CTRL 0x7c /* DOCCS Control Register */
20 #define SCx200_GPIO_SIZE 0x2c /* Size of GPIO register block */
23 #define SCx200_CB_BASE_FIXED 0x9000 /* Base fixed at 0x9000 according to errata? */
26 #define SCx200_WDT_OFFSET 0x00 /* offset within configuration block */
27 #define SCx200_WDT_SIZE 0x05 /* size */
29 #define SCx200_WDT_WDTO 0x00 /* Time-Out Register */
30 #define SCx200_WDT_WDCNFG 0x02 /* Configuration Register */
31 #define SCx200_WDT_WDSTS 0x04 /* Status Register */
[all …]
/openbmc/linux/arch/mips/mm/
H A Dsc-ip22.c24 #define SC_SIZE 0x00080000
39 " li $1, 0x80 # Go 64 bit \n" in indy_sc_wipe()
43 " # Open code a dli $1, 0x9000000080000000 \n" in indy_sc_wipe()
49 " lui $1,0x9000 \n" in indy_sc_wipe()
50 " dsll $1,$1,0x10 \n" in indy_sc_wipe()
51 " ori $1,$1,0x8000 \n" in indy_sc_wipe()
52 " dsll $1,$1,0x10 \n" in indy_sc_wipe()
54 " or %0, $1 # first line to flush \n" in indy_sc_wipe()
58 "1: sw $0, 0(%0) \n" in indy_sc_wipe()
59 " bne %0, %1, 1b \n" in indy_sc_wipe()
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dstxssa8555.dts30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
[all …]
H A Dmpc832x_rdb.dts26 #size-cells = <0>;
28 PowerPC,8323@0 {
30 reg = <0x0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
43 reg = <0x00000000 0x04000000>;
51 ranges = <0x0 0xe0000000 0x00100000>;
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D197.out13 read 0/0 bytes at offset 0
14 0 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 2 GiB (0x80010000) bytes allocated at offset 0 bytes (0x0)
21 1023.938 MiB (0x3fff0000) bytes not allocated at offset 2 GiB (0x80010000)
22 64 KiB (0x10000) bytes allocated at offset 3 GiB (0xc0000000)
23 1023.938 MiB (0x3fff0000) bytes not allocated at offset 3 GiB (0xc0010000)
30 read 1024/1024 bytes at offset 0
32 1 KiB (0x400) bytes allocated at offset 0 bytes (0x0)
39 wrote 65536/65536 bytes at offset 0
45 28 KiB (0x7000) bytes not allocated at offset 0 bytes (0x0)
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dturingcc-qcs404.c24 .halt_reg = 0x5098,
27 .enable_reg = 0x5098,
28 .enable_mask = BIT(0),
37 .halt_reg = 0x9000,
40 .enable_reg = 0x9000,
41 .enable_mask = BIT(0),
50 .halt_reg = 0xb000,
53 .enable_reg = 0xb000,
54 .enable_mask = BIT(0),
63 .halt_reg = 0x10000,
[all …]
/openbmc/linux/sound/pci/au88x0/
H A Dau8820.h19 #define NR_ADB 0x10
20 #define NR_WT 0x20
21 #define NR_SRC 0x10
22 #define NR_A3D 0x00
23 #define NR_MIXIN 0x10
24 #define NR_MIXOUT 0x10
28 #define VORTEX_ADBDMA_STAT 0x105c0 /* read only, subbuffer, DMA pos */
29 #define POS_MASK 0x00000fff
30 #define POS_SHIFT 0x0
31 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
[all …]
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos850.dtsi52 #clock-cells = <0>;
57 #size-cells = <0>;
91 cpu0: cpu@0 {
94 reg = <0x0>;
100 reg = <0x1>;
106 reg = <0x2>;
112 reg = <0x3>;
118 reg = <0x100>;
124 reg = <0x101>;
130 reg = <0x102>;
[all …]
/openbmc/linux/arch/alpha/kernel/
H A Dpci_impl.h18 * Also, we start at 0x8000 or 0x9000, in hopes to get all devices'
19 * IO space areas allocated *before* 0xC000; this is because certain
21 * accesses to probe the bus. If a device's registers appear at 0xC000,
26 #define EISA_DEFAULT_IO_BASE 0x9000 /* start above 8th slot */
27 #define DEFAULT_IO_BASE 0x8000 /* start at 8th slot */
107 * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
137 #define IOMMU_INVALID_PTE 0x2 /* 32:63 bits MBZ */
138 #define IOMMU_RESERVED_PTE 0xface
163 #define pci_restore_srm_config() do {} while (0)
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,msm8998-gpucc.yaml64 reg = <0x05065000 0x9000>;
H A Dqcom,sm6115-gpucc.yaml49 reg = <0x05990000 0x9000>;
H A Dqcom,sm6125-gpucc.yaml57 reg = <0x05990000 0x9000>;
/openbmc/u-boot/configs/
H A Ddra7xx_hs_evm_defconfig5 CONFIG_SYS_MALLOC_F_LEN=0x18000
7 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
8 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
9 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
41 CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000
58 CONFIG_FASTBOOT_BUF_ADDR=0x82000000
59 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
75 CONFIG_SF_DEFAULT_MODE=0
109 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
110 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
H A Ddra7xx_evm_defconfig4 CONFIG_SYS_MALLOC_F_LEN=0x18000
37 CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000
54 CONFIG_FASTBOOT_BUF_ADDR=0x82000000
55 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
71 CONFIG_SF_DEFAULT_MODE=0
105 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
106 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dplatform.h18 #define ASPEED_SDRAM_CTRL 0x1e6e0000
19 #define ASPEED_HW_STRAP1 0x1e6e2070
20 #define ASPEED_REVISION_ID 0x1e6e207C
21 #define ASPEED_SYS_RESET_CTRL 0x1e6e203C
22 #define ASPEED_VGA_HANDSHAKE0 0x1e6e2040 /* VGA function handshake register */
23 #define ASPEED_PCIE_CONFIG_SET 0x1e6e2180
24 #define ASPEED_DRAM_BASE 0x40000000
25 #define ASPEED_SRAM_BASE 0x1E720000
26 #define ASPEED_LPC_CTRL 0x1e789000
27 #define ASPEED_SRAM_SIZE 0x8000
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Domap24xx.h19 #define L4_24XX_BASE 0x48000000
20 #define L4_WK_243X_BASE 0x49000000
21 #define L3_24XX_BASE 0x68000000
24 #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
25 #define OMAP24XX_IVA_INTC_BASE 0x40000000
28 #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
29 #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
30 #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
32 #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
33 #define OMAP2420_SMS_BASE 0x68008000
[all …]

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