1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21da177e4SLinus Torvalds /* linux/include/linux/scx200.h 31da177e4SLinus Torvalds 41da177e4SLinus Torvalds Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com> 51da177e4SLinus Torvalds 61da177e4SLinus Torvalds Defines for the National Semiconductor SCx200 Processors 71da177e4SLinus Torvalds */ 81da177e4SLinus Torvalds 91da177e4SLinus Torvalds /* Interesting stuff for the National Semiconductor SCx200 CPU */ 101da177e4SLinus Torvalds 111da177e4SLinus Torvalds extern unsigned scx200_cb_base; 121da177e4SLinus Torvalds 131da177e4SLinus Torvalds #define scx200_cb_present() (scx200_cb_base!=0) 141da177e4SLinus Torvalds 151da177e4SLinus Torvalds /* F0 PCI Header/Bridge Configuration Registers */ 161da177e4SLinus Torvalds #define SCx200_DOCCS_BASE 0x78 /* DOCCS Base Address Register */ 171da177e4SLinus Torvalds #define SCx200_DOCCS_CTRL 0x7c /* DOCCS Control Register */ 181da177e4SLinus Torvalds 191da177e4SLinus Torvalds /* GPIO Register Block */ 201da177e4SLinus Torvalds #define SCx200_GPIO_SIZE 0x2c /* Size of GPIO register block */ 211da177e4SLinus Torvalds 221da177e4SLinus Torvalds /* General Configuration Block */ 231da177e4SLinus Torvalds #define SCx200_CB_BASE_FIXED 0x9000 /* Base fixed at 0x9000 according to errata? */ 241da177e4SLinus Torvalds 251da177e4SLinus Torvalds /* Watchdog Timer */ 261da177e4SLinus Torvalds #define SCx200_WDT_OFFSET 0x00 /* offset within configuration block */ 271da177e4SLinus Torvalds #define SCx200_WDT_SIZE 0x05 /* size */ 281da177e4SLinus Torvalds 291da177e4SLinus Torvalds #define SCx200_WDT_WDTO 0x00 /* Time-Out Register */ 301da177e4SLinus Torvalds #define SCx200_WDT_WDCNFG 0x02 /* Configuration Register */ 311da177e4SLinus Torvalds #define SCx200_WDT_WDSTS 0x04 /* Status Register */ 321da177e4SLinus Torvalds #define SCx200_WDT_WDSTS_WDOVF (1<<0) /* Overflow bit */ 331da177e4SLinus Torvalds 341da177e4SLinus Torvalds /* High Resolution Timer */ 351da177e4SLinus Torvalds #define SCx200_TIMER_OFFSET 0x08 36856fe98fSJim Cromie #define SCx200_TIMER_SIZE 0x06 371da177e4SLinus Torvalds 381da177e4SLinus Torvalds /* Clock Generators */ 391da177e4SLinus Torvalds #define SCx200_CLOCKGEN_OFFSET 0x10 401da177e4SLinus Torvalds #define SCx200_CLOCKGEN_SIZE 0x10 411da177e4SLinus Torvalds 421da177e4SLinus Torvalds /* Pin Multiplexing and Miscellaneous Configuration Registers */ 431da177e4SLinus Torvalds #define SCx200_MISC_OFFSET 0x30 441da177e4SLinus Torvalds #define SCx200_MISC_SIZE 0x10 451da177e4SLinus Torvalds 461da177e4SLinus Torvalds #define SCx200_PMR 0x30 /* Pin Multiplexing Register */ 471da177e4SLinus Torvalds #define SCx200_MCR 0x34 /* Miscellaneous Configuration Register */ 481da177e4SLinus Torvalds #define SCx200_INTSEL 0x38 /* Interrupt Selection Register */ 491da177e4SLinus Torvalds #define SCx200_IID 0x3c /* IA On a Chip Identification Number Reg */ 501da177e4SLinus Torvalds #define SCx200_REV 0x3d /* Revision Register */ 511da177e4SLinus Torvalds #define SCx200_CBA 0x3e /* Configuration Base Address Register */ 521da177e4SLinus Torvalds #define SCx200_CBA_SCRATCH 0x64 /* Configuration Base Address Scratchpad */ 53