/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | sc8280xp-pmics.dtsi | 14 polling-delay = <0>; 20 hysteresis = <0>; 26 hysteresis = <0>; 34 polling-delay = <0>; 40 hysteresis = <0>; 46 hysteresis = <0>; 55 pmk8280: pmic@0 { 57 reg = <0x0 SPMI_USID>; 59 #size-cells = <0>; 63 reg = <0x1300>, <0x800>; [all …]
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/openbmc/linux/drivers/soc/ux500/ |
H A D | ux500-soc-id.c | 25 * @process: the manufacturing process, 0x40 is 40 nm 0x00 is "standard" 26 * @partnumber: hithereto 0x8500 for DB8500 43 return 0; in ux500_read_asicid() 57 if (rev == 0x01) in ux500_print_soc_info() 59 else if (rev >= 0xA0) in ux500_print_soc_info() 60 pr_cont("v%d.%d" , (rev >> 4) - 0xA + 1, rev & 0xf); in ux500_print_soc_info() 69 return (asicid >> 8) & 0xffff; in partnumber() 74 * DB8500ed 0x410fc090 0x9001FFF4 0x00850001 75 * DB8500v1 0x411fc091 0x9001FFF4 0x008500A0 76 * DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1 [all …]
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/openbmc/linux/arch/arm/mach-omap2/ |
H A D | prcm43xx.h | 15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000 16 #define AM43XX_PRM_MPU_INST 0x0300 17 #define AM43XX_PRM_GFX_INST 0x0400 18 #define AM43XX_PRM_RTC_INST 0x0500 19 #define AM43XX_PRM_TAMPER_INST 0x0600 20 #define AM43XX_PRM_CEFUSE_INST 0x0700 21 #define AM43XX_PRM_PER_INST 0x0800 22 #define AM43XX_PRM_WKUP_INST 0x2000 23 #define AM43XX_PRM_DEVICE_INST 0x4000 26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004 [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | socionext,uniphier-ave4.yaml | 120 reg = <0x65000000 0x8500>; 121 interrupts = <0 66 4>; 128 socionext,syscon-phy-mode = <&soc_glue 0>; 132 #size-cells = <0>;
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/openbmc/linux/drivers/media/usb/gspca/ |
H A D | spca561.c | 37 #define Rev012A 0 64 .priv = 0}, 87 .priv = 0}, 112 #define SPCA561_INDEX_I2C_BASE 0x8800 113 #define SPCA561_SNAPBIT 0x20 114 #define SPCA561_SNAPCTRL 0x40 117 {0x0000, 0x8114}, /* Software GPIO output data */ 118 {0x0001, 0x8114}, /* Software GPIO output data */ 119 {0x0000, 0x8112}, /* Some kind of reset */ 123 {0x0003, 0x8701}, /* PCLK clock delay adjustment */ [all …]
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/openbmc/linux/include/video/ |
H A D | trident.h | 4 #define TRIDENTFB_DEBUG 0 20 #define CYBER9320 0x9320 21 #define CYBER9388 0x9388 22 #define CYBER9382 0x9382 /* the real PCI id for this is 9660 */ 23 #define CYBER9385 0x9385 /* ditto */ 24 #define CYBER9397 0x9397 25 #define CYBER9397DVD 0x939A 26 #define CYBER9520 0x9520 27 #define CYBER9525DVD 0x9525 28 #define TGUI9440 0x9440 [all …]
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/openbmc/linux/drivers/media/dvb-frontends/ |
H A D | stv6111.c | 37 { 2572, 0 }, 73 { 1548, 0 }, 109 { 4870, 0x3000 }, 110 { 4850, 0x3C00 }, 111 { 4800, 0x4500 }, 112 { 4750, 0x4800 }, 113 { 4700, 0x4B00 }, 114 { 4650, 0x4D00 }, 115 { 4600, 0x4F00 }, 116 { 4550, 0x5100 }, [all …]
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/openbmc/linux/tools/perf/tests/attr/ |
H A D | test-stat-default | 33 type=0 34 config=0 40 type=0 46 type=0 53 type=0 60 type=0 67 type=0 71 # PERF_TYPE_RAW / slots (0x400) 80 # PERF_TYPE_RAW / topdown-retiring (0x8000) 86 disabled=0 [all …]
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H A D | test-stat-detailed-1 | 34 type=0 35 config=0 41 type=0 48 type=0 55 type=0 62 type=0 69 type=0 73 # PERF_TYPE_RAW / slots (0x400) 82 # PERF_TYPE_RAW / topdown-retiring (0x8000) 88 disabled=0 [all …]
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H A D | test-stat-detailed-2 | 34 type=0 35 config=0 41 type=0 48 type=0 55 type=0 62 type=0 69 type=0 73 # PERF_TYPE_RAW / slots (0x400) 82 # PERF_TYPE_RAW / topdown-retiring (0x8000) 88 disabled=0 [all …]
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/openbmc/libmctp/ |
H A D | crc-16-ccitt.c | 12 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, 0x8c48, 13 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, 0x1081, 0x0108, 14 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, 0x9cc9, 0x8d40, 0xbfdb, 15 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, 0x2102, 0x308b, 0x0210, 0x1399, 16 0x6726, 0x76af, 0x4434, 0x55bd, 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 17 0xfae7, 0xc87c, 0xd9f5, 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 18 0x54b5, 0x453c, 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 19 0xc974, 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, 20 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, 0x5285, 21 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, 0xdecd, 0xcf44, [all …]
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/openbmc/linux/drivers/gpu/drm/i915/ |
H A D | vlv_suspend.c | 117 /* GAM 0x4000-0x4770 */ in vlv_save_gunit_s0ix_state() 124 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) in vlv_save_gunit_s0ix_state() 137 /* MBC 0x9024-0x91D0, 0x8500 */ in vlv_save_gunit_s0ix_state() 142 /* GCP 0x9400-0x9424, 0x8100-0x810C */ in vlv_save_gunit_s0ix_state() 150 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ in vlv_save_gunit_s0ix_state() 162 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ in vlv_save_gunit_s0ix_state() 168 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) in vlv_save_gunit_s0ix_state() 171 /* GT SA CZ domain, 0x100000-0x138124 */ in vlv_save_gunit_s0ix_state() 178 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ in vlv_save_gunit_s0ix_state() 186 * DFT, 0x9800-0x9EC0 in vlv_save_gunit_s0ix_state() [all …]
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/openbmc/u-boot/board/terasic/de0-nano-soc/qts/ |
H A D | sdram_config.h | 10 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 11 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 12 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 18 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 35 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 43 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 44 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 45 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 [all …]
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/openbmc/u-boot/board/ebv/socrates/qts/ |
H A D | sdram_config.h | 10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A 11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 [all …]
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/openbmc/u-boot/board/devboards/dbm-soc1/qts/ |
H A D | sdram_config.h | 10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A 11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 [all …]
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/openbmc/u-boot/board/samtec/vining_fpga/qts/ |
H A D | sdram_config.h | 10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A 11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 [all …]
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/openbmc/u-boot/board/sr1500/qts/ |
H A D | sdram_config.h | 10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A 11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 [all …]
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/openbmc/u-boot/board/terasic/de1-soc/qts/ |
H A D | sdram_config.h | 10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A 11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 [all …]
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/openbmc/u-boot/board/terasic/sockit/qts/ |
H A D | sdram_config.h | 10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A 11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 [all …]
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/openbmc/u-boot/board/is1/qts/ |
H A D | sdram_config.h | 10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A 11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 [all …]
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/openbmc/u-boot/board/altera/cyclone5-socdk/qts/ |
H A D | sdram_config.h | 10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A 11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 [all …]
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/openbmc/u-boot/board/terasic/de10-nano/qts/ |
H A D | sdram_config.h | 10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A 11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 [all …]
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/openbmc/u-boot/board/altera/arria5-socdk/qts/ |
H A D | sdram_config.h | 10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A 11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 [all …]
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/openbmc/linux/arch/powerpc/boot/dts/ |
H A D | ep8248e.dts | 26 #size-cells = <0>; 28 PowerPC,8248@0 { 30 reg = <0>; 35 timebase-frequency = <0>; 36 clock-frequency = <0>; 46 reg = <0xf0010100 0x40>; 48 ranges = <0 0 0xfc000000 0x04000000 49 1 0 0xfa000000 0x00008000>; 51 flash@0,3800000 { 53 reg = <0 0x3800000 0x800000>; [all …]
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/openbmc/linux/drivers/clk/imx/ |
H A D | clk-imx93.c | 58 { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL }, 59 { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, 60 { IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL }, 61 { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, 62 { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, 63 { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, 64 { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL }, 65 { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, }, 66 { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, }, 67 { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, }, [all …]
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