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/openbmc/linux/drivers/media/i2c/cx25840/
H A Dcx25840-firmware.c34 /* DL_ADDR_LB=0 DL_ADDR_HB=0 */ in start_fw_load()
35 cx25840_write(client, 0x800, 0x00); in start_fw_load()
36 cx25840_write(client, 0x801, 0x00); in start_fw_load()
37 // DL_MAP=3 DL_AUTO_INC=0 DL_ENABLE=1 in start_fw_load()
38 cx25840_write(client, 0x803, 0x0b); in start_fw_load()
40 cx25840_write(client, 0x000, 0x20); in start_fw_load()
45 /* AUTO_INC_DIS=0 */ in end_fw_load()
46 cx25840_write(client, 0x000, 0x00); in end_fw_load()
47 /* DL_ENABLE=0 */ in end_fw_load()
48 cx25840_write(client, 0x803, 0x03); in end_fw_load()
[all …]
/openbmc/linux/arch/m68k/mac/
H A Dmacboing.c23 static __u8 mac_asc_wave_tab[ 0x800 ];
26 * Alan's original sine table; needs interpolating to 0x800
27 * (hint: interpolate or hardwire [0 -> Pi/2[, it's symmetric)
30 0, 39, 75, 103, 121, 127, 121, 103, 75, 39,
31 0, -39, -75, -103, -121, -127, -121, -103, -75, -39
37 static volatile __u8* mac_asc_regs = ( void* )0x50F14000;
44 static unsigned long mac_bell_phase; /* 0..2*Pi -> 0..0x800 (wavetable size) */
74 * mac_asc_regs[ 0x800 ] & 0xF0 != 0 in mac_init_asc()
84 mac_asc_regs = ( void* )0x50010000; in mac_init_asc()
147 for ( i = 0; i < 0x400; i++ ) in mac_init_asc()
[all …]
/openbmc/qemu/hw/alpha/
H A Dtyphoon.c81 uint64_t ret = 0; in cchip_read()
84 case 0x0000: in cchip_read()
87 PIP<14> Pchip 1 Present = 0. */ in cchip_read()
90 case 0x0040: in cchip_read()
95 case 0x0080: in cchip_read()
100 case 0x00c0: in cchip_read()
104 case 0x0100: /* AAR0 */ in cchip_read()
105 case 0x0140: /* AAR1 */ in cchip_read()
106 case 0x0180: /* AAR2 */ in cchip_read()
107 case 0x01c0: /* AAR3 */ in cchip_read()
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dmac_asc.h13 #define ASC_BUF_BASE 0x00 /* RAM buffer offset */
14 #define ASC_BUF_SIZE 0x800
16 #define ASC_CONTROL 0x800
17 #define ASC_CONTROL_OFF 0x00
18 #define ASC_FREQ(chan,byte) ((0x810)+((chan)<<3)+(byte))
19 #define ASC_ENABLE 0x801
20 #define ASC_ENABLE_SAMPLE 0x02
21 #define ASC_MODE 0x802
22 #define ASC_MODE_SAMPLE 0x02
24 #define ASC_VOLUME 0x806
[all …]
/openbmc/linux/arch/arm/configs/
H A Dnetwinder_defconfig8 CONFIG_CMDLINE="root=0x801"
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_ti814x.c17 #define PRCM_MOD_EN 0x2
20 #define OSC_SRC0 0
32 #define SELFREQDCO_HS2 0x00000801
33 #define SELFREQDCO_HS1 0x00001001
35 #define MPU_N 0x1
36 #define MPU_M 0x3C
38 #define MPU_CLKCTRL 0x1
43 #define L3_CLKCTRL 0x801
48 #define DDR_CLKCTRL 0x801
51 #define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Dcs553x_nand.c11 * mtd-id for command line partitioning is cs553x_nand_cs[0-3]
12 * where 0-3 reflects the chip select for NAND.
29 #define MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */
30 #define CAP_CS5535 0x2df000ULL
31 #define CAP_CS5536 0x5df500ULL
34 #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
35 #define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
36 #define MSR_NANDF_RSVD 0x5140001d /* Reserved */
39 #define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */
40 #define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */
[all …]
/openbmc/linux/arch/parisc/kernel/
H A Dhardware.c29 {HPHW_NPROC,0x01,0x4,0x0,"Indigo (840, 930)"},
30 {HPHW_NPROC,0x8,0x4,0x01,"Firefox(825,925)"},
31 {HPHW_NPROC,0xA,0x4,0x01,"Top Gun (835,834,935,635)"},
32 {HPHW_NPROC,0xB,0x4,0x01,"Technical Shogun (845, 645)"},
33 {HPHW_NPROC,0xF,0x4,0x01,"Commercial Shogun (949)"},
34 {HPHW_NPROC,0xC,0x4,0x01,"Cheetah (850, 950)"},
35 {HPHW_NPROC,0x80,0x4,0x01,"Cheetah (950S)"},
36 {HPHW_NPROC,0x81,0x4,0x01,"Jaguar (855, 955)"},
37 {HPHW_NPROC,0x82,0x4,0x01,"Cougar (860, 960)"},
38 {HPHW_NPROC,0x83,0x4,0x13,"Panther (865, 870, 980)"},
[all …]
/openbmc/linux/drivers/mfd/
H A Dwm5110-tables.c22 { 0x80, 0x3 },
23 { 0x44, 0x20 },
24 { 0x45, 0x40 },
25 { 0x46, 0x60 },
26 { 0x47, 0x80 },
27 { 0x48, 0xa0 },
28 { 0x51, 0x13 },
29 { 0x52, 0x33 },
30 { 0x53, 0x53 },
31 { 0x54, 0x73 },
[all …]
H A Drz-mtu3.c28 /******* MTU3 registers (original offset is +0x1200) *******/
30 [RZ_MTU3_CHAN_0] = MTU_8BIT_CH_0(0x104, 0x090, 0x100, 0x128, 0x101, 0x102, 0x103, 0x126),
31 [RZ_MTU3_CHAN_1] = MTU_8BIT_CH_1_2(0x184, 0x091, 0x185, 0x180, 0x194, 0x181, 0x182),
32 [RZ_MTU3_CHAN_2] = MTU_8BIT_CH_1_2(0x204, 0x092, 0x205, 0x200, 0x20c, 0x201, 0x202),
33 …[RZ_MTU3_CHAN_3] = MTU_8BIT_CH_3_4_6_7(0x008, 0x093, 0x02c, 0x000, 0x04c, 0x002, 0x004, 0x005, 0x0…
34 …[RZ_MTU3_CHAN_4] = MTU_8BIT_CH_3_4_6_7(0x009, 0x094, 0x02d, 0x001, 0x04d, 0x003, 0x006, 0x007, 0x0…
35 …[RZ_MTU3_CHAN_5] = MTU_8BIT_CH_5(0xab2, 0x1eb, 0xab4, 0xab6, 0xa84, 0xa85, 0xa86, 0xa94, 0xa95, 0x…
36 …[RZ_MTU3_CHAN_6] = MTU_8BIT_CH_3_4_6_7(0x808, 0x893, 0x82c, 0x800, 0x84c, 0x802, 0x804, 0x805, 0x8…
37 …[RZ_MTU3_CHAN_7] = MTU_8BIT_CH_3_4_6_7(0x809, 0x894, 0x82d, 0x801, 0x84d, 0x803, 0x806, 0x807, 0x8…
38 [RZ_MTU3_CHAN_8] = MTU_8BIT_CH_8(0x404, 0x098, 0x400, 0x406, 0x401, 0x402, 0x403)
[all …]
/openbmc/linux/tools/arch/arm64/include/asm/
H A Dcputype.h10 #define MPIDR_UP_BITMASK (0x1 << 30)
11 #define MPIDR_MT_BITMASK (0x1 << 24)
12 #define MPIDR_HWID_BITMASK UL(0xff00ffffff)
24 #define MIDR_REVISION_MASK 0xf
27 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
31 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
35 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
39 #define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT)
45 (0xf << MIDR_ARCHITECTURE_SHIFT) | \
54 #define ARM_CPU_IMP_ARM 0x41
[all …]
/openbmc/linux/arch/arm64/include/asm/
H A Dcputype.h10 #define MPIDR_UP_BITMASK (0x1 << 30)
11 #define MPIDR_MT_BITMASK (0x1 << 24)
12 #define MPIDR_HWID_BITMASK UL(0xff00ffffff)
24 #define MIDR_REVISION_MASK 0xf
27 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
31 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
35 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
39 #define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT)
45 (0xf << MIDR_ARCHITECTURE_SHIFT) | \
54 #define ARM_CPU_IMP_ARM 0x41
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sm8250-camss.yaml113 port@0:
308 reg = <0 0xac6a000 0 0x2000>,
309 <0 0xac6c000 0 0x2000>,
310 <0 0xac6e000 0 0x1000>,
311 <0 0xac70000 0 0x1000>,
312 <0 0xac72000 0 0x1000>,
313 <0 0xac74000 0 0x1000>,
314 <0 0xacb4000 0 0xd000>,
315 <0 0xacc3000 0 0xd000>,
316 <0 0xacd9000 0 0x2200>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/apple/
H A Dt6002.dtsi70 reg = <0x0 0x800>;
72 cpu-release-addr = <0 0>; /* To be filled by loader */
74 i-cache-size = <0x20000>;
75 d-cache-size = <0x10000>;
84 reg = <0x0 0x801>;
86 cpu-release-addr = <0 0>; /* To be filled by loader */
88 i-cache-size = <0x20000>;
89 d-cache-size = <0x10000>;
98 reg = <0x0 0x10900>;
100 cpu-release-addr = <0 0>; /* To be filled by loader */
[all …]
/openbmc/linux/drivers/input/keyboard/
H A Dhilkbd.c44 #define HIL_DATA 0x800
45 #define HIL_CMD 0x801
52 #define HILBASE 0xf0428000UL /* HP300 (m68k) port address */
53 #define HIL_DATA 0x1
54 #define HIL_CMD 0x3
70 #define hil_command(x) do { hil_writeb((x), HILBASE + HIL_CMD); } while (0)
72 #define hil_write_data(x) do { hil_writeb((x), HILBASE + HIL_DATA); } while (0)
76 #define HIL_BUSY 0x02
77 #define HIL_DATA_RDY 0x01
79 #define HIL_SETARD 0xA0 /* set auto-repeat delay */
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-core.h32 CX18_AV_SVIDEO_LUMA1 = 0x10,
33 CX18_AV_SVIDEO_LUMA2 = 0x20,
34 CX18_AV_SVIDEO_LUMA3 = 0x30,
35 CX18_AV_SVIDEO_LUMA4 = 0x40,
36 CX18_AV_SVIDEO_LUMA5 = 0x50,
37 CX18_AV_SVIDEO_LUMA6 = 0x60,
38 CX18_AV_SVIDEO_LUMA7 = 0x70,
39 CX18_AV_SVIDEO_LUMA8 = 0x80,
40 CX18_AV_SVIDEO_CHROMA4 = 0x400,
41 CX18_AV_SVIDEO_CHROMA5 = 0x500,
[all …]
/openbmc/linux/include/linux/bcma/
H A Dbcma_driver_pci.h10 #define BCMA_CORE_PCI_CTL 0x0000 /* PCI Control */
11 #define BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
12 #define BCMA_CORE_PCI_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
13 #define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
14 #define BCMA_CORE_PCI_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
15 #define BCMA_CORE_PCI_ARBCTL 0x0010 /* PCI Arbiter Control */
16 #define BCMA_CORE_PCI_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
17 #define BCMA_CORE_PCI_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
18 #define BCMA_CORE_PCI_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle …
19 #define BCMA_CORE_PCI_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
[all …]
H A Dbcma.h62 #define BCMA_MANUF_ARM 0x43B
63 #define BCMA_MANUF_MIPS 0x4A7
64 #define BCMA_MANUF_BCM 0x4BF
67 #define BCMA_CL_SIM 0x0
68 #define BCMA_CL_EROM 0x1
69 #define BCMA_CL_CORESIGHT 0x9
70 #define BCMA_CL_VERIF 0xB
71 #define BCMA_CL_OPTIMO 0xD
72 #define BCMA_CL_GEN 0xE
73 #define BCMA_CL_PRIMECELL 0xF
[all …]
/openbmc/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpni-cmd.h13 #define DPNI_VER_MINOR 0
23 #define DPNI_CMDID_OPEN DPNI_CMD(0x801)
24 #define DPNI_CMDID_CLOSE DPNI_CMD(0x800)
25 #define DPNI_CMDID_CREATE DPNI_CMD(0x901)
26 #define DPNI_CMDID_DESTROY DPNI_CMD(0x900)
27 #define DPNI_CMDID_GET_API_VERSION DPNI_CMD(0xa01)
29 #define DPNI_CMDID_ENABLE DPNI_CMD(0x002)
30 #define DPNI_CMDID_DISABLE DPNI_CMD(0x003)
31 #define DPNI_CMDID_GET_ATTR DPNI_CMD(0x004)
32 #define DPNI_CMDID_RESET DPNI_CMD(0x005)
[all …]
/openbmc/linux/include/uapi/linux/
H A Delf.h26 #define PT_NULL 0
34 #define PT_LOOS 0x60000000 /* OS-specific */
35 #define PT_HIOS 0x6fffffff /* OS-specific */
36 #define PT_LOPROC 0x70000000
37 #define PT_HIPROC 0x7fffffff
38 #define PT_GNU_EH_FRAME (PT_LOOS + 0x474e550)
39 #define PT_GNU_STACK (PT_LOOS + 0x474e551)
40 #define PT_GNU_RELRO (PT_LOOS + 0x474e552)
41 #define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
45 #define PT_AARCH64_MEMTAG_MTE (PT_LOPROC + 0x2)
[all …]
/openbmc/linux/drivers/bus/fsl-mc/
H A Dfsl-mc-private.h27 #define DPMNG_CMDID_GET_VERSION DPMNG_CMD(0x831)
41 #define DPMCP_MIN_VER_MINOR 0
50 #define DPMCP_CMDID_CLOSE DPMCP_CMD(0x800)
51 #define DPMCP_CMDID_RESET DPMCP_CMD(0x005)
79 #define DPRC_MIN_VER_MINOR 0
92 #define DPRC_CMDID_CLOSE DPRC_CMD(0x800)
93 #define DPRC_CMDID_GET_API_VERSION DPRC_CMD(0xa05)
95 #define DPRC_CMDID_GET_ATTR DPRC_CMD(0x004)
96 #define DPRC_CMDID_RESET_CONT DPRC_CMD(0x005)
97 #define DPRC_CMDID_RESET_CONT_V2 DPRC_CMD_V2(0x005)
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_GECC2 0x9c9
36 #define mmMC_ARB_GECC2_CLI 0x9ca
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7_ppsmc.h30 #define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
32 #define PPSMC_SWSTATE_FLAG_DC 0x01
33 #define PPSMC_SWSTATE_FLAG_UVD 0x02
34 #define PPSMC_SWSTATE_FLAG_VCE 0x04
36 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
37 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
38 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
40 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
41 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
42 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
/openbmc/linux/drivers/media/usb/go7007/
H A Ds2250-board.c26 #define TLV320_ADDRESS 0x34
27 #define VPX322_ADDR_ANALOGCONTROL1 0x02
28 #define VPX322_ADDR_BRIGHTNESS0 0x0127
29 #define VPX322_ADDR_BRIGHTNESS1 0x0131
30 #define VPX322_ADDR_CONTRAST0 0x0128
31 #define VPX322_ADDR_CONTRAST1 0x0132
32 #define VPX322_ADDR_HUE 0x00dc
33 #define VPX322_ADDR_SAT 0x0030
50 0x1e, 0x00,
51 0x00, 0x17,
[all …]
/openbmc/qemu/target/m68k/
H A Dcpu.h28 #define OS_BYTE 0
54 #define EXCP_TRAP0 32 /* User trap #0. */
68 #define EXCP_RTE 0x100
69 #define EXCP_SEMIHOSTING 0x101
71 #define M68K_DTTR0 0
101 uint32_t cc_x; /* always 0/1 */
104 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
105 uint32_t cc_z; /* == 0 or unused */
227 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */
233 #define CCF_C 0x01
[all …]

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