1*837d542aSEvan Quan /* 2*837d542aSEvan Quan * Copyright 2015 Advanced Micro Devices, Inc. 3*837d542aSEvan Quan * 4*837d542aSEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5*837d542aSEvan Quan * copy of this software and associated documentation files (the "Software"), 6*837d542aSEvan Quan * to deal in the Software without restriction, including without limitation 7*837d542aSEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*837d542aSEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9*837d542aSEvan Quan * Software is furnished to do so, subject to the following conditions: 10*837d542aSEvan Quan * 11*837d542aSEvan Quan * The above copyright notice and this permission notice shall be included in 12*837d542aSEvan Quan * all copies or substantial portions of the Software. 13*837d542aSEvan Quan * 14*837d542aSEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*837d542aSEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*837d542aSEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*837d542aSEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*837d542aSEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*837d542aSEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*837d542aSEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21*837d542aSEvan Quan * 22*837d542aSEvan Quan */ 23*837d542aSEvan Quan 24*837d542aSEvan Quan #ifndef DGPU_VI_PP_SMC_H 25*837d542aSEvan Quan #define DGPU_VI_PP_SMC_H 26*837d542aSEvan Quan 27*837d542aSEvan Quan 28*837d542aSEvan Quan #pragma pack(push, 1) 29*837d542aSEvan Quan 30*837d542aSEvan Quan #define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305) 31*837d542aSEvan Quan 32*837d542aSEvan Quan #define PPSMC_SWSTATE_FLAG_DC 0x01 33*837d542aSEvan Quan #define PPSMC_SWSTATE_FLAG_UVD 0x02 34*837d542aSEvan Quan #define PPSMC_SWSTATE_FLAG_VCE 0x04 35*837d542aSEvan Quan 36*837d542aSEvan Quan #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 37*837d542aSEvan Quan #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 38*837d542aSEvan Quan #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff 39*837d542aSEvan Quan 40*837d542aSEvan Quan #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 41*837d542aSEvan Quan #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 42*837d542aSEvan Quan #define PPSMC_SYSTEMFLAG_GDDR5 0x04 43*837d542aSEvan Quan 44*837d542aSEvan Quan #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 45*837d542aSEvan Quan 46*837d542aSEvan Quan #define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 47*837d542aSEvan Quan #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 48*837d542aSEvan Quan 49*837d542aSEvan Quan #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 50*837d542aSEvan Quan #define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 51*837d542aSEvan Quan 52*837d542aSEvan Quan #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 53*837d542aSEvan Quan #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 54*837d542aSEvan Quan 55*837d542aSEvan Quan 56*837d542aSEvan Quan #define PPSMC_DPM2FLAGS_TDPCLMP 0x01 57*837d542aSEvan Quan #define PPSMC_DPM2FLAGS_PWRSHFT 0x02 58*837d542aSEvan Quan #define PPSMC_DPM2FLAGS_OCP 0x04 59*837d542aSEvan Quan 60*837d542aSEvan Quan 61*837d542aSEvan Quan #define PPSMC_DISPLAY_WATERMARK_LOW 0 62*837d542aSEvan Quan #define PPSMC_DISPLAY_WATERMARK_HIGH 1 63*837d542aSEvan Quan 64*837d542aSEvan Quan 65*837d542aSEvan Quan #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 66*837d542aSEvan Quan #define PPSMC_STATEFLAG_POWERBOOST 0x02 67*837d542aSEvan Quan #define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04 68*837d542aSEvan Quan #define PPSMC_STATEFLAG_POWERSHIFT 0x08 69*837d542aSEvan Quan #define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10 70*837d542aSEvan Quan #define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 71*837d542aSEvan Quan #define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 72*837d542aSEvan Quan 73*837d542aSEvan Quan 74*837d542aSEvan Quan #define FDO_MODE_HARDWARE 0 75*837d542aSEvan Quan #define FDO_MODE_PIECE_WISE_LINEAR 1 76*837d542aSEvan Quan 77*837d542aSEvan Quan enum FAN_CONTROL { 78*837d542aSEvan Quan FAN_CONTROL_FUZZY, 79*837d542aSEvan Quan FAN_CONTROL_TABLE 80*837d542aSEvan Quan }; 81*837d542aSEvan Quan 82*837d542aSEvan Quan 83*837d542aSEvan Quan #define PPSMC_Result_OK ((uint16_t)0x01) 84*837d542aSEvan Quan #define PPSMC_Result_NoMore ((uint16_t)0x02) 85*837d542aSEvan Quan 86*837d542aSEvan Quan #define PPSMC_Result_NotNow ((uint16_t)0x03) 87*837d542aSEvan Quan #define PPSMC_Result_Failed ((uint16_t)0xFF) 88*837d542aSEvan Quan #define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) 89*837d542aSEvan Quan #define PPSMC_Result_UnknownVT ((uint16_t)0xFD) 90*837d542aSEvan Quan 91*837d542aSEvan Quan typedef uint16_t PPSMC_Result; 92*837d542aSEvan Quan 93*837d542aSEvan Quan #define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) 94*837d542aSEvan Quan 95*837d542aSEvan Quan 96*837d542aSEvan Quan #define PPSMC_MSG_Halt ((uint16_t)0x10) 97*837d542aSEvan Quan #define PPSMC_MSG_Resume ((uint16_t)0x11) 98*837d542aSEvan Quan #define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12) 99*837d542aSEvan Quan #define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13) 100*837d542aSEvan Quan #define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14) 101*837d542aSEvan Quan #define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15) 102*837d542aSEvan Quan #define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16) 103*837d542aSEvan Quan #define PPSMC_MSG_RunningOnAC ((uint16_t)0x17) 104*837d542aSEvan Quan #define PPSMC_MSG_LevelUp ((uint16_t)0x18) 105*837d542aSEvan Quan #define PPSMC_MSG_LevelDown ((uint16_t)0x19) 106*837d542aSEvan Quan #define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a) 107*837d542aSEvan Quan #define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20) 108*837d542aSEvan Quan #define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f) 109*837d542aSEvan Quan #define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40) 110*837d542aSEvan Quan #define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41) 111*837d542aSEvan Quan #define PPSMC_MSG_ForceHigh ((uint16_t)0x42) 112*837d542aSEvan Quan #define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43) 113*837d542aSEvan Quan #define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51) 114*837d542aSEvan Quan #define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52) 115*837d542aSEvan Quan #define PPSMC_MSG_EnableCac ((uint16_t)0x53) 116*837d542aSEvan Quan #define PPSMC_MSG_DisableCac ((uint16_t)0x54) 117*837d542aSEvan Quan #define PPSMC_DPMStateHistoryStart ((uint16_t)0x55) 118*837d542aSEvan Quan #define PPSMC_DPMStateHistoryStop ((uint16_t)0x56) 119*837d542aSEvan Quan #define PPSMC_CACHistoryStart ((uint16_t)0x57) 120*837d542aSEvan Quan #define PPSMC_CACHistoryStop ((uint16_t)0x58) 121*837d542aSEvan Quan #define PPSMC_TDPClampingActive ((uint16_t)0x59) 122*837d542aSEvan Quan #define PPSMC_TDPClampingInactive ((uint16_t)0x5A) 123*837d542aSEvan Quan #define PPSMC_StartFanControl ((uint16_t)0x5B) 124*837d542aSEvan Quan #define PPSMC_StopFanControl ((uint16_t)0x5C) 125*837d542aSEvan Quan #define PPSMC_NoDisplay ((uint16_t)0x5D) 126*837d542aSEvan Quan #define PPSMC_HasDisplay ((uint16_t)0x5E) 127*837d542aSEvan Quan #define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60) 128*837d542aSEvan Quan #define PPSMC_MSG_UVDPowerON ((uint16_t)0x61) 129*837d542aSEvan Quan #define PPSMC_MSG_EnableULV ((uint16_t)0x62) 130*837d542aSEvan Quan #define PPSMC_MSG_DisableULV ((uint16_t)0x63) 131*837d542aSEvan Quan #define PPSMC_MSG_EnterULV ((uint16_t)0x64) 132*837d542aSEvan Quan #define PPSMC_MSG_ExitULV ((uint16_t)0x65) 133*837d542aSEvan Quan #define PPSMC_PowerShiftActive ((uint16_t)0x6A) 134*837d542aSEvan Quan #define PPSMC_PowerShiftInactive ((uint16_t)0x6B) 135*837d542aSEvan Quan #define PPSMC_OCPActive ((uint16_t)0x6C) 136*837d542aSEvan Quan #define PPSMC_OCPInactive ((uint16_t)0x6D) 137*837d542aSEvan Quan #define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E) 138*837d542aSEvan Quan #define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F) 139*837d542aSEvan Quan #define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70) 140*837d542aSEvan Quan #define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71) 141*837d542aSEvan Quan #define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72) 142*837d542aSEvan Quan #define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73) 143*837d542aSEvan Quan #define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74) 144*837d542aSEvan Quan #define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75) 145*837d542aSEvan Quan #define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76) 146*837d542aSEvan Quan #define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77) 147*837d542aSEvan Quan #define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78) 148*837d542aSEvan Quan #define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79) 149*837d542aSEvan Quan #define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A) 150*837d542aSEvan Quan #define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B) 151*837d542aSEvan Quan #define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C) 152*837d542aSEvan Quan #define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D) 153*837d542aSEvan Quan 154*837d542aSEvan Quan #define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E) 155*837d542aSEvan Quan #define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F) 156*837d542aSEvan Quan #define PPSMC_FlushDataCache ((uint16_t)0x80) 157*837d542aSEvan Quan #define PPSMC_FlushInstrCache ((uint16_t)0x81) 158*837d542aSEvan Quan 159*837d542aSEvan Quan #define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82) 160*837d542aSEvan Quan #define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83) 161*837d542aSEvan Quan 162*837d542aSEvan Quan #define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84) 163*837d542aSEvan Quan 164*837d542aSEvan Quan #define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85) 165*837d542aSEvan Quan #define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86) 166*837d542aSEvan Quan #define PPSMC_MSG_EnableDTE ((uint16_t)0x87) 167*837d542aSEvan Quan #define PPSMC_MSG_DisableDTE ((uint16_t)0x88) 168*837d542aSEvan Quan 169*837d542aSEvan Quan #define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89) 170*837d542aSEvan Quan #define PPSM_MSG_SmcSpaceWriteDWordInc ((uint16_t)0x8A) 171*837d542aSEvan Quan #define PPSM_MSG_SmcSpaceWriteWordInc ((uint16_t)0x8B) 172*837d542aSEvan Quan #define PPSM_MSG_SmcSpaceWriteByteInc ((uint16_t)0x8C) 173*837d542aSEvan Quan 174*837d542aSEvan Quan #define PPSMC_MSG_BREAK ((uint16_t)0xF8) 175*837d542aSEvan Quan 176*837d542aSEvan Quan #define PPSMC_MSG_Test ((uint16_t) 0x100) 177*837d542aSEvan Quan #define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101) 178*837d542aSEvan Quan #define PPSMC_MSG_DPM_Config ((uint16_t) 0x102) 179*837d542aSEvan Quan #define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103) 180*837d542aSEvan Quan #define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104) 181*837d542aSEvan Quan #define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105) 182*837d542aSEvan Quan #define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106) 183*837d542aSEvan Quan #define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107) 184*837d542aSEvan Quan #define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108) 185*837d542aSEvan Quan #define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109) 186*837d542aSEvan Quan #define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a) 187*837d542aSEvan Quan #define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b) 188*837d542aSEvan Quan #define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e) 189*837d542aSEvan Quan #define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f) 190*837d542aSEvan Quan #define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110) 191*837d542aSEvan Quan #define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111) 192*837d542aSEvan Quan #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112) 193*837d542aSEvan Quan #define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113) 194*837d542aSEvan Quan #define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114) 195*837d542aSEvan Quan #define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117) 196*837d542aSEvan Quan #define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118) 197*837d542aSEvan Quan #define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119) 198*837d542aSEvan Quan #define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a) 199*837d542aSEvan Quan #define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b) 200*837d542aSEvan Quan #define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c) 201*837d542aSEvan Quan #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d) 202*837d542aSEvan Quan #define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e) 203*837d542aSEvan Quan #define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f) 204*837d542aSEvan Quan #define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120) 205*837d542aSEvan Quan #define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121) 206*837d542aSEvan Quan #define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122) 207*837d542aSEvan Quan #define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123) 208*837d542aSEvan Quan #define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124) 209*837d542aSEvan Quan #define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125) 210*837d542aSEvan Quan #define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126) 211*837d542aSEvan Quan #define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127) 212*837d542aSEvan Quan #define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128) 213*837d542aSEvan Quan 214*837d542aSEvan Quan #define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129) 215*837d542aSEvan Quan #define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A) 216*837d542aSEvan Quan #define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B) 217*837d542aSEvan Quan #define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C) 218*837d542aSEvan Quan #define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) 219*837d542aSEvan Quan #define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) 220*837d542aSEvan Quan #define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) 221*837d542aSEvan Quan #define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) 222*837d542aSEvan Quan #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) 223*837d542aSEvan Quan #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) 224*837d542aSEvan Quan #define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) 225*837d542aSEvan Quan #define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134) 226*837d542aSEvan Quan #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) 227*837d542aSEvan Quan #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) 228*837d542aSEvan Quan #define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) 229*837d542aSEvan Quan #define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) 230*837d542aSEvan Quan #define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) 231*837d542aSEvan Quan #define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) 232*837d542aSEvan Quan #define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b) 233*837d542aSEvan Quan #define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c) 234*837d542aSEvan Quan #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) 235*837d542aSEvan Quan #define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e) 236*837d542aSEvan Quan #define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f) 237*837d542aSEvan Quan #define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) 238*837d542aSEvan Quan #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) 239*837d542aSEvan Quan #define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142) 240*837d542aSEvan Quan #define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143) 241*837d542aSEvan Quan #define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144) 242*837d542aSEvan Quan #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) 243*837d542aSEvan Quan #define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) 244*837d542aSEvan Quan #define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) 245*837d542aSEvan Quan #define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) 246*837d542aSEvan Quan #define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149) 247*837d542aSEvan Quan #define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) 248*837d542aSEvan Quan #define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b) 249*837d542aSEvan Quan #define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c) 250*837d542aSEvan Quan #define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d) 251*837d542aSEvan Quan 252*837d542aSEvan Quan #define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e) 253*837d542aSEvan Quan #define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f) 254*837d542aSEvan Quan #define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150) 255*837d542aSEvan Quan #define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151) 256*837d542aSEvan Quan #define PPSMC_MSG_LCLKDPM_Enable ((uint16_t) 0x152) 257*837d542aSEvan Quan #define PPSMC_MSG_LCLKDPM_Disable ((uint16_t) 0x153) 258*837d542aSEvan Quan #define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154) 259*837d542aSEvan Quan #define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155) 260*837d542aSEvan Quan #define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156) 261*837d542aSEvan Quan #define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157) 262*837d542aSEvan Quan #define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158) 263*837d542aSEvan Quan #define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159) 264*837d542aSEvan Quan #define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a) 265*837d542aSEvan Quan #define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b) 266*837d542aSEvan Quan #define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t) 0x15c) 267*837d542aSEvan Quan #define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d) 268*837d542aSEvan Quan #define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e) 269*837d542aSEvan Quan #define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) 270*837d542aSEvan Quan #define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160) 271*837d542aSEvan Quan #define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161) 272*837d542aSEvan Quan #define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) 273*837d542aSEvan Quan #define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163) 274*837d542aSEvan Quan #define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164) 275*837d542aSEvan Quan #define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165) 276*837d542aSEvan Quan #define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166) 277*837d542aSEvan Quan #define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) 278*837d542aSEvan Quan #define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168) 279*837d542aSEvan Quan #define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) 280*837d542aSEvan Quan #define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) 281*837d542aSEvan Quan #define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b) 282*837d542aSEvan Quan #define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t) 0x16c) 283*837d542aSEvan Quan #define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t) 0x16d) 284*837d542aSEvan Quan #define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t) 0x16e) 285*837d542aSEvan Quan #define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t) 0x16f) 286*837d542aSEvan Quan #define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170) 287*837d542aSEvan Quan #define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171) 288*837d542aSEvan Quan #define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172) 289*837d542aSEvan Quan #define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173) 290*837d542aSEvan Quan #define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174) 291*837d542aSEvan Quan #define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175) 292*837d542aSEvan Quan #define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176) 293*837d542aSEvan Quan #define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177) 294*837d542aSEvan Quan #define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178) 295*837d542aSEvan Quan #define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179) 296*837d542aSEvan Quan #define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a) 297*837d542aSEvan Quan #define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b) 298*837d542aSEvan Quan #define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c) 299*837d542aSEvan Quan #define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d) 300*837d542aSEvan Quan #define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e) 301*837d542aSEvan Quan #define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f) 302*837d542aSEvan Quan #define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180) 303*837d542aSEvan Quan #define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181) 304*837d542aSEvan Quan #define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182) 305*837d542aSEvan Quan #define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184) 306*837d542aSEvan Quan #define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) 307*837d542aSEvan Quan #define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) 308*837d542aSEvan Quan #define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) 309*837d542aSEvan Quan #define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) 310*837d542aSEvan Quan #define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) 311*837d542aSEvan Quan #define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) 312*837d542aSEvan Quan #define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) 313*837d542aSEvan Quan #define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) 314*837d542aSEvan Quan #define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D) 315*837d542aSEvan Quan #define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E) 316*837d542aSEvan Quan #define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) 317*837d542aSEvan Quan #define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) 318*837d542aSEvan Quan #define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) 319*837d542aSEvan Quan #define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192) 320*837d542aSEvan Quan #define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193) 321*837d542aSEvan Quan #define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194) 322*837d542aSEvan Quan #define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195) 323*837d542aSEvan Quan #define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207) 324*837d542aSEvan Quan #define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196) 325*837d542aSEvan Quan #define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208) 326*837d542aSEvan Quan #define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197) 327*837d542aSEvan Quan #define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198) 328*837d542aSEvan Quan #define PPSMC_MSG_SetTjMax ((uint16_t) 0x199) 329*837d542aSEvan Quan #define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) 330*837d542aSEvan Quan #define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B) 331*837d542aSEvan Quan #define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) 332*837d542aSEvan Quan #define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) 333*837d542aSEvan Quan 334*837d542aSEvan Quan #define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) 335*837d542aSEvan Quan #define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) 336*837d542aSEvan Quan #define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202) 337*837d542aSEvan Quan #define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203) 338*837d542aSEvan Quan #define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204) 339*837d542aSEvan Quan #define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205) 340*837d542aSEvan Quan #define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206) 341*837d542aSEvan Quan #define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209) 342*837d542aSEvan Quan #define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A) 343*837d542aSEvan Quan 344*837d542aSEvan Quan #define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240) 345*837d542aSEvan Quan #define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241) 346*837d542aSEvan Quan #define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242) 347*837d542aSEvan Quan #define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243) 348*837d542aSEvan Quan #define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244) 349*837d542aSEvan Quan #define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245) 350*837d542aSEvan Quan #define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246) 351*837d542aSEvan Quan 352*837d542aSEvan Quan #define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250) 353*837d542aSEvan Quan #define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251) 354*837d542aSEvan Quan #define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252) 355*837d542aSEvan Quan #define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253) 356*837d542aSEvan Quan #define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254) 357*837d542aSEvan Quan #define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255) 358*837d542aSEvan Quan #define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256) 359*837d542aSEvan Quan #define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257) 360*837d542aSEvan Quan #define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258) 361*837d542aSEvan Quan #define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259) 362*837d542aSEvan Quan #define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A) 363*837d542aSEvan Quan #define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B) 364*837d542aSEvan Quan #define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C) 365*837d542aSEvan Quan #define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D) 366*837d542aSEvan Quan #define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260) 367*837d542aSEvan Quan #define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261) 368*837d542aSEvan Quan #define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262) 369*837d542aSEvan Quan #define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263) 370*837d542aSEvan Quan #define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264) 371*837d542aSEvan Quan #define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265) 372*837d542aSEvan Quan #define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266) 373*837d542aSEvan Quan #define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267) 374*837d542aSEvan Quan #define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268) 375*837d542aSEvan Quan #define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269) 376*837d542aSEvan Quan #define PPSMC_MSG_EnableAvfs ((uint16_t) 0x26A) 377*837d542aSEvan Quan #define PPSMC_MSG_DisableAvfs ((uint16_t) 0x26B) 378*837d542aSEvan Quan 379*837d542aSEvan Quan #define PPSMC_MSG_PerformBtc ((uint16_t) 0x26C) 380*837d542aSEvan Quan #define PPSMC_MSG_LedConfig ((uint16_t) 0x274) 381*837d542aSEvan Quan #define PPSMC_MSG_VftTableIsValid ((uint16_t) 0x275) 382*837d542aSEvan Quan #define PPSMC_MSG_UseNewGPIOScheme ((uint16_t) 0x277) 383*837d542aSEvan Quan #define PPSMC_MSG_GetEnabledPsm ((uint16_t) 0x400) 384*837d542aSEvan Quan #define PPSMC_MSG_AgmStartPsm ((uint16_t) 0x401) 385*837d542aSEvan Quan #define PPSMC_MSG_AgmReadPsm ((uint16_t) 0x402) 386*837d542aSEvan Quan #define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403) 387*837d542aSEvan Quan #define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404) 388*837d542aSEvan Quan 389*837d542aSEvan Quan #define PPSMC_MSG_ApplyAvfsCksOffVoltage ((uint16_t) 0x415) 390*837d542aSEvan Quan 391*837d542aSEvan Quan #define PPSMC_MSG_GFX_CU_PG_ENABLE ((uint16_t) 0x280) 392*837d542aSEvan Quan #define PPSMC_MSG_GFX_CU_PG_DISABLE ((uint16_t) 0x281) 393*837d542aSEvan Quan #define PPSMC_MSG_GetCurrPkgPwr ((uint16_t) 0x282) 394*837d542aSEvan Quan 395*837d542aSEvan Quan #define PPSMC_MSG_SetGpuPllDfsForSclk ((uint16_t) 0x300) 396*837d542aSEvan Quan #define PPSMC_MSG_Didt_Block_Function ((uint16_t) 0x301) 397*837d542aSEvan Quan #define PPSMC_MSG_EnableZeroRpm ((uint16_t) 0x302) 398*837d542aSEvan Quan 399*837d542aSEvan Quan #define PPSMC_MSG_SetVBITimeout ((uint16_t) 0x306) 400*837d542aSEvan Quan 401*837d542aSEvan Quan #define PPSMC_MSG_EnableFFC ((uint16_t) 0x307) 402*837d542aSEvan Quan #define PPSMC_MSG_DisableFFC ((uint16_t) 0x308) 403*837d542aSEvan Quan 404*837d542aSEvan Quan #define PPSMC_MSG_EnableDpmDidt ((uint16_t) 0x309) 405*837d542aSEvan Quan #define PPSMC_MSG_DisableDpmDidt ((uint16_t) 0x30A) 406*837d542aSEvan Quan #define PPSMC_MSG_EnableDpmMcBlackout ((uint16_t) 0x30B) 407*837d542aSEvan Quan #define PPSMC_MSG_DisableDpmMcBlackout ((uint16_t) 0x30C) 408*837d542aSEvan Quan 409*837d542aSEvan Quan #define PPSMC_MSG_EnableEDCController ((uint16_t) 0x316) 410*837d542aSEvan Quan #define PPSMC_MSG_DisableEDCController ((uint16_t) 0x317) 411*837d542aSEvan Quan 412*837d542aSEvan Quan #define PPSMC_MSG_SecureSRBMWrite ((uint16_t) 0x600) 413*837d542aSEvan Quan #define PPSMC_MSG_SecureSRBMRead ((uint16_t) 0x601) 414*837d542aSEvan Quan #define PPSMC_MSG_SetAddress ((uint16_t) 0x800) 415*837d542aSEvan Quan #define PPSMC_MSG_GetData ((uint16_t) 0x801) 416*837d542aSEvan Quan #define PPSMC_MSG_SetData ((uint16_t) 0x802) 417*837d542aSEvan Quan 418*837d542aSEvan Quan typedef uint16_t PPSMC_Msg; 419*837d542aSEvan Quan 420*837d542aSEvan Quan #define PPSMC_EVENT_STATUS_THERMAL 0x00000001 421*837d542aSEvan Quan #define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002 422*837d542aSEvan Quan #define PPSMC_EVENT_STATUS_DC 0x00000004 423*837d542aSEvan Quan 424*837d542aSEvan Quan #pragma pack(pop) 425*837d542aSEvan Quan 426*837d542aSEvan Quan #endif 427*837d542aSEvan Quan 428