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/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-base.h21 #define MXS_ICOLL_BASE 0x80000000
22 #define MXS_APBH_BASE 0x80004000
23 #define MXS_ECC8_BASE 0x80008000
24 #define MXS_BCH_BASE 0x8000A000
25 #define MXS_GPMI_BASE 0x8000C000
26 #define MXS_SSP0_BASE 0x80010000
27 #define MXS_SSP1_BASE 0x80034000
28 #define MXS_ETM_BASE 0x80014000
29 #define MXS_PINCTRL_BASE 0x80018000
30 #define MXS_DIGCTL_BASE 0x8001C000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,mxs-dma.yaml60 reg = <0x80004000 0x2000>;
64 87 86 0 0>;
71 reg = <0x80024000 0x2000>;
72 interrupts = <78 79 66 0
/openbmc/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23.dtsi32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
45 reg = <0x80000000 0x80000>;
52 reg = <0x80000000 0x40000>;
59 reg = <0x80000000 0x2000>;
64 reg = <0x80004000 0x2000>;
65 interrupts = <0>, <14>, <20>, <0>,
73 reg = <0x80008000 0x2000>;
81 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
[all …]
H A Dimx28.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
56 reg = <0x80000000 0x80000>;
63 reg = <0x80000000 0x3c900>;
70 reg = <0x80000000 0x2000>;
74 reg = <0x80002000 0x2000>;
83 reg = <0x80004000 0x2000>;
87 <87>, <86>, <0>, <0>;
94 reg = <0x80006000 0x800>;
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dregs.h37 #define MT_HW_REV MT_HW_INFO(0x000)
38 #define MT_HW_CHIPID MT_HW_INFO(0x008)
39 #define MT_TOP_STRAP_STA MT_HW_INFO(0x010)
42 #define MT_TOP_OFF_RSV 0x1128
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
46 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
51 #define MT_MCU_BASE 0x2000
54 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
55 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
57 #define MT_PCIE_REMAP_BASE_1 0x40000
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dregs.h6 #define MT_HW_REV 0x1000
7 #define MT_HW_CHIPID 0x1008
8 #define MT_TOP_MISC2 0x1134
10 #define MT_MCU_BASE 0x2000
13 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
17 #define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
21 #define MT_HIF_BASE 0x4000
24 #define MT_INT_SOURCE_CSR MT_HIF(0x200)
[all …]
/openbmc/linux/arch/arm/
H A DKconfig.debug149 0x80000000 | 0xf0000000 | UART0
150 0x80004000 | 0xf0004000 | UART1
151 0x80008000 | 0xf0008000 | UART2
152 0x8000c000 | 0xf000c000 | UART3
153 0x80010000 | 0xf0010000 | UART4
154 0x80014000 | 0xf0014000 | UART5
155 0x80018000 | 0xf0018000 | UART6
156 0x8001c000 | 0xf001c000 | UART7
157 0x80020000 | 0xf0020000 | UART8
158 0x80024000 | 0xf0024000 | UART9
[all …]