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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,sparx5-switch.yaml34 pattern: "^switch@[0-9a-f]+$"
83 const: 0
86 "^port@[0-9a-f]+$":
111 minimum: 0
142 reg = <0 0x401000>,
143 <0x10004000 0x7fc000>,
144 <0x11010000 0xaf0000>;
148 resets = <&reset 0>;
152 #size-cells = <0>;
154 port0: port@0 {
[all …]
/openbmc/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi28 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0x0>;
49 reg = <0x1>;
81 #clock-cells = <0>;
89 reg = <0x6 0x1110000c 0x24>;
94 #clock-cells = <0>;
100 #clock-cells = <0>;
116 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
117 <0x6 0x00340000 0xc0000>, /* GICR */
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8994-msft-lumia-octagon.dtsi51 #clock-cells = <0>;
57 pinctrl-0 = <&divclk4_pin_a>;
97 pinctrl-0 = <&hall_front_default &hall_back_default>;
128 reg = <0 0x00200000 0 0x100000>;
133 reg = <0 0x00300000 0 0x80000>;
138 reg = <0 0x00380000 0 0x1000>;
143 reg = <0 0x00381000 0 0x4000>;
148 reg = <0 0x00385000 0 0x1000>;
153 reg = <0 0x00386000 0 0x3000>;
158 reg = <0 0x00389000 0 0x1000>;
[all …]
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]