/openbmc/linux/arch/sh/include/cpu-sh4a/cpu/ |
H A D | dma.h | 9 #define DMTE0_IRQ evt2irq(0x800) 10 #define DMTE4_IRQ evt2irq(0xb80) 11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ 12 #define SH_DMAC_BASE0 0xFE008020 14 #define DMTE0_IRQ evt2irq(0x800) 15 #define DMTE4_IRQ evt2irq(0xb80) 16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ 17 #define SH_DMAC_BASE0 0xFE008020 19 #define DMTE0_IRQ evt2irq(0x640) 20 #define DMTE4_IRQ evt2irq(0x780) [all …]
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/openbmc/linux/arch/sh/kernel/cpu/sh4/ |
H A D | setup-sh4-202.c | 23 DEFINE_RES_MEM(0xffe80000, 0x100), 24 DEFINE_RES_IRQ(evt2irq(0x700)), 25 DEFINE_RES_IRQ(evt2irq(0x720)), 26 DEFINE_RES_IRQ(evt2irq(0x760)), 27 DEFINE_RES_IRQ(evt2irq(0x740)), 32 .id = 0, 45 DEFINE_RES_MEM(0xffd80000, 0x30), 46 DEFINE_RES_IRQ(evt2irq(0x400)), 47 DEFINE_RES_IRQ(evt2irq(0x420)), 48 DEFINE_RES_IRQ(evt2irq(0x440)), [all …]
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H A D | setup-sh7750.c | 19 [0] = { 20 .start = 0xffc80000, 21 .end = 0xffc80000 + 0x58 - 1, 26 .start = evt2irq(0x480), 43 DEFINE_RES_MEM(0xffe00000, 0x20), 44 DEFINE_RES_IRQ(evt2irq(0x4e0)), 49 .id = 0, 63 DEFINE_RES_MEM(0xffe80000, 0x100), 64 DEFINE_RES_IRQ(evt2irq(0x700)), 82 DEFINE_RES_MEM(0xffd80000, 0x30), [all …]
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/openbmc/linux/drivers/pinctrl/mediatek/ |
H A D | pinctrl-mt8365.c | 18 /* 0E4E8SR 4/8/12/16 */ 20 /* 0E2E4SR 2/4/6/8 */ 23 MTK_DRV_GRP(2, 16, 0, 2, 2) 28 MTK_PIN_DRV_GRP(0, 0x710, 0, 2), 29 MTK_PIN_DRV_GRP(1, 0x710, 0, 2), 30 MTK_PIN_DRV_GRP(2, 0x710, 0, 2), 31 MTK_PIN_DRV_GRP(3, 0x710, 0, 2), 32 MTK_PIN_DRV_GRP(4, 0x710, 4, 2), 33 MTK_PIN_DRV_GRP(5, 0x710, 4, 2), 34 MTK_PIN_DRV_GRP(6, 0x710, 4, 2), [all …]
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/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | amlogic,g12a-toacodec.yaml | 53 reg = <0x740 0x4>;
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/openbmc/linux/Documentation/devicetree/bindings/rtc/ |
H A D | amlogic,meson6-rtc.yaml | 51 reg = <0x740 0x14>; 59 mac@0 { 60 reg = <0 6>;
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/openbmc/linux/include/linux/usb/ |
H A D | usb338x.h | 19 #define SCRATCH 0x0b 36 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \ 38 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \ 45 #define DEVICE_CLASS 0 48 #define U1_SYSTEM_EXIT_LATENCY 0 51 #define U1_DEVICE_EXIT_LATENCY 0 55 #define USB_L1_LPM_SUPPORT 0 58 #define BEST_EFFORT_LATENCY_TOLERANCE 0 66 #define SERIAL_NUMBER_STRING_ENABLE 0 79 #define GPEP0_TIMEOUT_ENABLE 0 [all …]
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/openbmc/linux/arch/sh/kernel/cpu/sh4a/ |
H A D | setup-shx3.c | 20 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2 34 DEFINE_RES_MEM(0xffc30000, 0x100), 35 DEFINE_RES_IRQ(evt2irq(0x700)), 36 DEFINE_RES_IRQ(evt2irq(0x720)), 37 DEFINE_RES_IRQ(evt2irq(0x760)), 38 DEFINE_RES_IRQ(evt2irq(0x740)), 43 .id = 0, 57 DEFINE_RES_MEM(0xffc40000, 0x100), 58 DEFINE_RES_IRQ(evt2irq(0x780)), 59 DEFINE_RES_IRQ(evt2irq(0x7a0)), [all …]
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H A D | setup-sh7786.c | 35 DEFINE_RES_MEM(0xffea0000, 0x100), 36 DEFINE_RES_IRQ(evt2irq(0x700)), 37 DEFINE_RES_IRQ(evt2irq(0x720)), 38 DEFINE_RES_IRQ(evt2irq(0x760)), 39 DEFINE_RES_IRQ(evt2irq(0x740)), 44 .id = 0, 62 DEFINE_RES_MEM(0xffeb0000, 0x100), 63 DEFINE_RES_IRQ(evt2irq(0x780)), 67 DEFINE_RES_MEM(0xffeb0000, 0x100), 69 DEFINE_RES_IRQ(0), [all …]
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/openbmc/u-boot/board/ti/ti814x/ |
H A D | evm.c | 35 .cmd0csratio = 0x80, 36 .cmd0iclkout = 0x00, 38 .cmd1csratio = 0x80, 39 .cmd1iclkout = 0x00, 41 .cmd2csratio = 0x80, 42 .cmd2iclkout = 0x00, 46 .sdram_config = 0x40801ab2, 47 .ref_ctrl = 0x10000c30, 48 .sdram_tim1 = 0x0aaaf552, 49 .sdram_tim2 = 0x043631d2, [all …]
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/openbmc/linux/arch/arm/include/asm/hardware/ |
H A D | cache-l2x0.h | 15 #define L2X0_CACHE_ID 0x000 16 #define L2X0_CACHE_TYPE 0x004 17 #define L2X0_CTRL 0x100 18 #define L2X0_AUX_CTRL 0x104 19 #define L310_TAG_LATENCY_CTRL 0x108 20 #define L310_DATA_LATENCY_CTRL 0x10C 21 #define L2X0_EVENT_CNT_CTRL 0x200 22 #define L2X0_EVENT_CNT1_CFG 0x204 23 #define L2X0_EVENT_CNT0_CFG 0x208 24 #define L2X0_EVENT_CNT1_VAL 0x20C [all …]
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/openbmc/qemu/hw/intc/ |
H A D | pnv_xive_regs.h | 13 /* IC register offsets 0x0 - 0x400 */ 14 #define CQ_SWI_CMD_HIST 0x020 15 #define CQ_SWI_CMD_POLL 0x028 16 #define CQ_SWI_CMD_BCAST 0x030 17 #define CQ_SWI_CMD_ASSIGN 0x038 18 #define CQ_SWI_CMD_BLK_UPD 0x040 19 #define CQ_SWI_RSP 0x048 20 #define CQ_CFG_PB_GEN 0x050 22 #define CQ_MSGSND 0x058 23 #define CQ_CNPM_SEL 0x078 [all …]
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/openbmc/linux/drivers/net/ethernet/apple/ |
H A D | bmac.h | 17 #define XIFC 0x000 /* low-level interface control */ 18 # define TxOutputEnable 0x0001 /* output driver enable */ 19 # define XIFLoopback 0x0002 /* Loopback-mode XIF enable */ 20 # define MIILoopback 0x0004 /* Loopback-mode MII enable */ 21 # define MIILoopbackBits 0x0006 22 # define MIIBuffDisable 0x0008 /* MII receive buffer disable */ 23 # define SQETestEnable 0x0010 /* SQE test enable */ 24 # define SQETimeWindow 0x03e0 /* SQE time window */ 25 # define XIFLanceMode 0x0010 /* Lance mode enable */ 26 # define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */ [all …]
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/openbmc/u-boot/drivers/mtd/nand/raw/ |
H A D | denali.h | 14 #define DEVICE_RESET 0x0 17 #define TRANSFER_SPARE_REG 0x10 18 #define TRANSFER_SPARE_REG__FLAG BIT(0) 20 #define LOAD_WAIT_CNT 0x20 21 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0) 23 #define PROGRAM_WAIT_CNT 0x30 24 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0) 26 #define ERASE_WAIT_CNT 0x40 27 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0) 29 #define INT_MON_CYCCNT 0x50 [all …]
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/openbmc/linux/arch/arm/boot/dts/amlogic/ |
H A D | meson.dtsi | 28 reg = <0xc1100000 0x200000>; 31 ranges = <0x0 0xc1100000 0x200000>; 37 reg = <0x4000 0x400>; 44 reg = <0x5400 0x2ac>; 53 reg = <0x7c00 0x200>; 58 reg = <0x8100 0x8>; 63 reg = <0x84c0 0x18>; 71 reg = <0x84dc 0x18>; 78 reg = <0x8500 0x20>; 81 #size-cells = <0>; [all …]
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/openbmc/linux/drivers/gpu/drm/radeon/ |
H A D | rv6xxd.h | 27 #define SPLL_CNTL_MODE 0x60c 30 #define GENERAL_PWRMGT 0x618 31 # define GLOBAL_PWRMGT_EN (1 << 0) 47 #define MCLK_PWRMGT_CNTL 0x624 48 # define MPLL_PWRMGT_OFF (1 << 0) 78 #define MPLL_FREQ_LEVEL_0 0x6e8 79 # define LEVEL0_MPLL_POST_DIV(x) ((x) << 0) 80 # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0) 82 # define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8) 84 # define LEVEL0_MPLL_REF_DIV_MASK (0x3f << 20) [all …]
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H A D | sumod.h | 30 #define RCU_FW_VERSION 0x30c 32 #define RCU_PWR_GATING_SEQ0 0x408 33 #define RCU_PWR_GATING_SEQ1 0x40c 34 #define RCU_PWR_GATING_CNTL 0x410 35 # define PWR_GATING_EN (1 << 0) 36 # define RSVD_MASK (0x3 << 1) 38 # define PCV_MASK (0x1f << 3) 41 # define PCP_MASK (0xf << 8) 44 # define RPW_MASK (0xf << 16) 47 # define ID_MASK (0xf << 24) [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx6q-pinfunc.h | 13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | imx6q-pinfunc.h | 17 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 18 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 19 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 20 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 21 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 22 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 23 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 24 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 25 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 26 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 [all …]
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/openbmc/linux/drivers/mtd/nand/raw/ |
H A D | denali.h | 17 #define DEVICE_RESET 0x0 20 #define TRANSFER_SPARE_REG 0x10 21 #define TRANSFER_SPARE_REG__FLAG BIT(0) 23 #define LOAD_WAIT_CNT 0x20 24 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0) 26 #define PROGRAM_WAIT_CNT 0x30 27 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0) 29 #define ERASE_WAIT_CNT 0x40 30 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0) 32 #define INT_MON_CYCCNT 0x50 [all …]
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/openbmc/linux/Documentation/devicetree/bindings/usb/ |
H A D | qcom,dwc3.yaml | 117 "^usb@[0-9a-f]+$": 495 reg = <0 0x0a6f8800 0 0x400>; 528 reg = <0 0x0a600000 0 0xcd00>; 530 iommus = <&apps_smmu 0x740 0>;
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/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/ |
H A D | immap_ls102xa.h | 10 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 11 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 12 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) 13 #define IS_E_PROCESSOR(svr) (svr & 0x80000) 17 #define SOC_VER_SLS1020 0x00 18 #define SOC_VER_LS1020 0x10 19 #define SOC_VER_LS1021 0x11 20 #define SOC_VER_LS1022 0x12 22 #define SOC_MAJOR_VER_1_0 0x1 23 #define SOC_MAJOR_VER_2_0 0x2 [all …]
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/openbmc/linux/arch/arm64/boot/dts/amlogic/ |
H A D | meson-g12.dtsi | 14 tdmif_a: audio-controller-0 { 16 #sound-dai-cells = <0>; 27 #sound-dai-cells = <0>; 38 #sound-dai-cells = <0>; 52 reg = <0x0 0x40000 0x0 0x34>; 53 #sound-dai-cells = <0>; 65 reg = <0x0 0x42000 0x0 0x2000>; 68 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 70 clkc_audio: clock-controller@0 { 73 reg = <0x0 0x0 0x0 0xb4>; [all …]
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/openbmc/u-boot/drivers/phy/marvell/ |
H A D | comphy_hpipe.h | 10 #define SD_EXTERNAL_CONFIG0_REG 0 16 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) 19 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) 31 (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) 33 #define SD_EXTERNAL_CONFIG1_REG 0x4 36 (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) 39 (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) 42 (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) 45 (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) 47 #define SD_EXTERNAL_CONFIG2_REG 0x8 [all …]
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/openbmc/qemu/hw/net/fsl_etsec/ |
H A D | registers.h | 49 #define DMACTRL_WOP (1 << 0) 51 #define IEVENT_PERR (1 << 0) 94 #define MACCFG1_TX_EN (1 << 0) 100 #define MIIMCOM_READ (1 << 0) 103 #define RCTRL_PRSDEP_MASK (0x3) 109 #define TSEC_ID (0x000 / 4) 110 #define TSEC_ID2 (0x004 / 4) 111 #define IEVENT (0x010 / 4) 112 #define IMASK (0x014 / 4) 113 #define EDIS (0x018 / 4) [all …]
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