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Searched +full:0 +full:x71200000 (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/hw/sparc/
H A Dsun4m.c74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
78 #define PROM_VADDR 0xffd00000
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
83 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
131 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { in DECLARE_CLASS_CHECKERS()
142 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); in fw_cfg_boot_set()
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/openbmc/linux/arch/arm/mach-s3c/
H A Dmap-s3c64xx.h22 #define S3C64XX_PA_XM0CSN0 (0x10000000)
23 #define S3C64XX_PA_XM0CSN1 (0x18000000)
24 #define S3C64XX_PA_XM0CSN2 (0x20000000)
25 #define S3C64XX_PA_XM0CSN3 (0x28000000)
26 #define S3C64XX_PA_XM0CSN4 (0x30000000)
27 #define S3C64XX_PA_XM0CSN5 (0x38000000)
30 #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
31 #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
35 #define S3C_PA_UART (0x7F005000)
36 #define S3C_PA_UART0 (S3C_PA_UART + 0x00)
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmscc,vsc7514-switch.yaml38 "^port@[0-9a-f]+$":
55 "^port@[0-9a-f]+$":
142 reg = <0x1010000 0x10000>,
143 <0x1030000 0x10000>,
144 <0x1080000 0x100>,
145 <0x10e0000 0x10000>,
146 <0x11e0000 0x100>,
147 <0x11f0000 0x100>,
148 <0x1200000 0x100>,
149 <0x1210000 0x100>,
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/openbmc/linux/arch/arm/boot/dts/samsung/
H A Ds3c64xx.dtsi33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0x0>;
51 reg = <0x71200000 0x1000>;
58 reg = <0x71300000 0x1000>;
64 reg = <0x7c200000 0x100>;
67 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
75 reg = <0x7c300000 0x100>;
78 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
86 reg = <0x7c400000 0x100>;
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/openbmc/linux/drivers/mfd/
H A Docelot-core.c31 #define REG_GCB_SOFT_RST 0x0008
33 #define BIT_SOFT_CHIP_RST BIT(0)
35 #define VSC7512_MIIM0_RES_START 0x7107009c
36 #define VSC7512_MIIM1_RES_START 0x710700c0
37 #define VSC7512_MIIM_RES_SIZE 0x00000024
39 #define VSC7512_PHY_RES_START 0x710700f0
40 #define VSC7512_PHY_RES_SIZE 0x00000004
42 #define VSC7512_GPIO_RES_START 0x71070034
43 #define VSC7512_GPIO_RES_SIZE 0x0000006c
45 #define VSC7512_SIO_CTRL_RES_START 0x710700f8
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/openbmc/qemu/tests/qtest/
H A Dm48t59-test.c19 #define RTC_SECONDS 0x9
20 #define RTC_MINUTES 0xa
21 #define RTC_HOURS 0xb
23 #define RTC_DAY_OF_WEEK 0xc
24 #define RTC_DAY_OF_MONTH 0xd
25 #define RTC_MONTH 0xe
26 #define RTC_YEAR 0xf
29 static uint16_t reg_base = 0x1ff0; /* 0x7f0 for m48t02 */
48 qtest_outw(s, base + 0, reg_base + (uint16_t)reg); in cmos_read_ioio()
54 qtest_outw(s, base + 0, reg_base + (uint16_t)reg); in cmos_write_ioio()
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