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/openbmc/linux/arch/arm/mach-omap2/
H A Domap34xx.h17 #define L4_34XX_BASE 0x48000000
18 #define L4_WK_34XX_BASE 0x48300000
19 #define L4_PER_34XX_BASE 0x49000000
20 #define L4_EMU_34XX_BASE 0x54000000
21 #define L3_34XX_BASE 0x68000000
23 #define L4_WK_AM33XX_BASE 0x44C00000
25 #define OMAP3430_32KSYNCT_BASE 0x48320000
26 #define OMAP3430_CM_BASE 0x48004800
27 #define OMAP3430_PRM_BASE 0x48306800
28 #define OMAP343X_SMS_BASE 0x6C000000
[all …]
H A Domap24xx.h19 #define L4_24XX_BASE 0x48000000
20 #define L4_WK_243X_BASE 0x49000000
21 #define L3_24XX_BASE 0x68000000
24 #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
25 #define OMAP24XX_IVA_INTC_BASE 0x40000000
28 #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
29 #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
30 #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
32 #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
33 #define OMAP2420_SMS_BASE 0x68008000
[all …]
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mips/cavium/
H A Dsata-uctl.txt30 reg = <0x11800 0x6c000000 0x0 0x100>;
38 reg = <0x16c00 0x00000000 0x0 0x200>;
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dst,stm32-fmc2-ebi.yaml46 <bank-number> 0 <address of the bank> <size>
49 "^.*@[0-4],[a-f0-9]+$":
73 reg = <0x58002000 0x1000>;
77 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
78 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
79 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
80 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
81 <4 0 0x80000000 0x10000000>; /* NAND */
83 psram@0,0 {
85 reg = <0 0x00000000 0x100000>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Domap.h15 #define SMX_APE_BASE 0x68000000
18 #define OMAP34XX_GPMC_BASE 0x6E000000
21 #define OMAP34XX_SMS_BASE 0x6C000000
24 #define OMAP34XX_SDRC_BASE 0x6D000000
29 #define OMAP34XX_CORE_L4_IO_BASE 0x48000000
30 #define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
31 #define OMAP34XX_ID_L4_IO_BASE 0x4830A200
32 #define OMAP34XX_L4_PER 0x49000000
36 #define OMAP34XX_DMA4_BASE 0x48056000
39 #define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dcpu_asm.h9 #define BIT_C 0x00000001
11 #define OP_BLR 0x4e800020
12 #define OP_EXTSB 0x7c000774
13 #define OP_EXTSH 0x7c000734
14 #define OP_NEG 0x7c0000d0
15 #define OP_CNTLZW 0x7c000034
16 #define OP_ADD 0x7c000214
17 #define OP_ADDC 0x7c000014
18 #define OP_ADDME 0x7c0001d4
19 #define OP_ADDZE 0x7c000194
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dfsl_epu.c13 {EPGCR, 0},
15 {EPECR0 + EPECR_STRIDE * 0, 0},
16 {EPECR0 + EPECR_STRIDE * 1, 0},
17 {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
18 {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
19 {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
20 {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
21 {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
22 {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
23 {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
[all …]
/openbmc/qemu/hw/sparc/
H A Dsun4m.c74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
78 #define PROM_VADDR 0xffd00000
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
83 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
131 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { in DECLARE_CLASS_CHECKERS()
142 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); in fw_cfg_boot_set()
[all …]
/openbmc/qemu/disas/
H A Dhppa.c50 #define PA_PAGESIZE 0x1000
59 R_HPPA_FSEL = 0x0,
60 R_HPPA_LSSEL = 0x1,
61 R_HPPA_RSSEL = 0x2,
62 R_HPPA_LSEL = 0x3,
63 R_HPPA_RSEL = 0x4,
64 R_HPPA_LDSEL = 0x5,
65 R_HPPA_RDSEL = 0x6,
66 R_HPPA_LRSEL = 0x7,
67 R_HPPA_RRSEL = 0x8,
[all …]
H A Dmicroblaze.c137 /* gen purpose regs go from 0 to 31 */
140 #define REG_PC_MASK 0x8000
141 #define REG_MSR_MASK 0x8001
142 #define REG_EAR_MASK 0x8003
143 #define REG_ESR_MASK 0x8005
144 #define REG_FSR_MASK 0x8007
145 #define REG_BTR_MASK 0x800b
146 #define REG_EDR_MASK 0x800d
147 #define REG_PVR_MASK 0xa000
149 #define REG_PID_MASK 0x9000
[all …]
H A Dmips.c82 #define OP_MASK_OP 0x3f
84 #define OP_MASK_RS 0x1f
86 #define OP_MASK_FR 0x1f
88 #define OP_MASK_FMT 0x1f
90 #define OP_MASK_BCC 0x7
92 #define OP_MASK_CODE 0x3ff
94 #define OP_MASK_CODE2 0x3ff
96 #define OP_MASK_RT 0x1f
98 #define OP_MASK_FT 0x1f
100 #define OP_MASK_CACHE 0x1f
[all …]
H A Dnanomips.c62 return g_strdup_printf("0x%" PRIx64, a); in to_string()
97 * 1 0
98 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
107 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
108 * 3 2 1 0
123 sizeof(register_list) / sizeof(register_list[0]), info); in decode_gpr_gpr4()
132 * 1 0
133 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
142 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
143 * 3 2 1 0
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi23 #size-cells = <0>;
270 reg = <0x10000>;
273 numa-node-id = <0>;
279 reg = <0x10001>;
282 numa-node-id = <0>;
288 reg = <0x10002>;
291 numa-node-id = <0>;
297 reg = <0x10003>;
300 numa-node-id = <0>;
306 reg = <0x10100>;
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dppc-opcode.h13 #define __REG_R0 0
46 #define __REGA0_0 0
80 #define _R0 0
113 #define IMM_L(i) ((uintptr_t)(i) & 0xffff)
114 #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
115 #define IMM_DQ(i) ((uintptr_t)(i) & 0xfff0)
116 #define IMM_D0(i) (((uintptr_t)(i) >> 16) & 0x3ffff)
122 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
128 (((uintptr_t)(i) & 0x8000) >> 15))
133 #define IMM_H18(i) (((uintptr_t)(i)>>16) & 0x3ffff)
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp131.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
43 #size-cells = <0>;
44 linaro,optee-channel-id = <0>;
47 reg = <0x14>;
52 reg = <0x16>;
57 reg = <0x17>;
61 #size-cells = <0>;
63 scmi_reg11: regulator@0 {
[all …]
H A Dstm32mp151.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
82 #clock-cells = <0>;
[all …]
/openbmc/linux/drivers/crypto/chelsio/
H A Dchcr_algo.c77 0, 0, 16, 24, 40, 48, 64, 72, 88,
84 0, 32, 32, 48, 48, 64, 64, 80, 80,
91 0x01000000, 0x02000000, 0x04000000, 0x08000000,
92 0x10000000, 0x20000000, 0x40000000, 0x80000000,
93 0x1B000000, 0x36000000, 0x6C000000
131 memset(&reqctx->hctx_wr, 0, sizeof(struct chcr_hctx_per_wr)); in chcr_init_hctx_per_wr()
138 int nents = 0; in sg_nents_xlen()
140 unsigned int skip_len = 0; in sg_nents_xlen()
145 skip_len = 0; in sg_nents_xlen()
149 skip = 0; in sg_nents_xlen()
[all …]
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc12 OPC_MOVGR2SCR = 0x00000800,
13 OPC_MOVSCR2GR = 0x00000c00,
14 OPC_CLZ_W = 0x00001400,
15 OPC_CTZ_W = 0x00001c00,
16 OPC_CLZ_D = 0x00002400,
17 OPC_CTZ_D = 0x00002c00,
18 OPC_REVB_2H = 0x00003000,
19 OPC_REVB_2W = 0x00003800,
20 OPC_REVB_D = 0x00003c00,
21 OPC_SEXT_H = 0x00005800,
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852b_table.c10 {0x704, 0x601E0100},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x44511475},
15 {0x4010, 0x00000000},
16 {0x4014, 0x00000000},
17 {0x4018, 0x4F4C084B},
18 {0x401C, 0x084A4E52},
19 {0x4020, 0x4D504E4B},
[all …]
H A Drtw8852a_table.c10 {0xF0FF0001, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03500FF, 0x00000002},
13 {0xF03200FF, 0x00000003},
14 {0xF03400FF, 0x00000004},
15 {0xF03600FF, 0x00000005},
16 {0x704, 0x601E0100},
17 {0x714, 0x00000000},
18 {0x718, 0x13332333},
19 {0x714, 0x00010000},
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]