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/openbmc/u-boot/include/configs/
H A Devb_rv1108.h16 "netdev=eth0\0" \
17 "ipaddr=172.16.12.50\0" \
18 "serverip=172.16.12.69\0" \
24 "sf read 0x62000000 0x140800 0x500000;" \
26 "go 0x62000000"
H A Drv1108_common.h17 #define CONFIG_SYS_TIMER_BASE 0x10350020
20 #define CONFIG_SYS_SDRAM_BASE 0x60000000
21 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
22 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000)
31 "scriptaddr=0x60000000\0" \
32 "fdt_addr_r=0x61f00000\0" \
33 "kernel_addr_r=0x62000000\0" \
34 "ramdisk_addr_r=0x64000000\0"
39 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
H A Drk3128_common.h18 #define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
21 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
22 #define CONFIG_SYS_LOAD_ADDR 0x60800800
30 #define CONFIG_SYS_SDRAM_BASE 0x60000000
31 #define SDRAM_MAX_SIZE 0x80000000
41 "scriptaddr=0x60500000\0" \
42 "pxefile_addr_r=0x60600000\0" \
43 "fdt_addr_r=0x61f00000\0" \
44 "kernel_addr_r=0x62000000\0" \
45 "ramdisk_addr_r=0x64000000\0"
[all …]
H A Drk3036_common.h16 #define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
19 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
20 #define CONFIG_SYS_LOAD_ADDR 0x60800800
21 #define CONFIG_SPL_STACK 0x10081fff
22 #define CONFIG_SPL_TEXT_BASE 0x10081000
27 #define CONFIG_SYS_SDRAM_BASE 0x60000000
41 "scriptaddr=0x60000000\0" \
42 "pxefile_addr_r=0x60100000\0" \
43 "fdt_addr_r=0x61f00000\0" \
44 "kernel_addr_r=0x62000000\0" \
[all …]
H A Drk3188_common.h21 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
23 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
24 #define CONFIG_SYS_LOAD_ADDR 0x60800800
26 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
29 #define CONFIG_SPL_TEXT_BASE 0x10080800
31 #define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
34 #define CONFIG_SPL_STACK 0x10087fff
36 #define CONFIG_SYS_SDRAM_BASE 0x60000000
38 #define SDRAM_MAX_SIZE 0x80000000
45 "scriptaddr=0x60000000\0" \
[all …]
H A Drk322x_common.h17 #define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */
20 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
21 #define CONFIG_SYS_LOAD_ADDR 0x60800800
22 #define CONFIG_SPL_STACK 0x10088000
23 #define CONFIG_SPL_TEXT_BASE 0x10081000
28 #define CONFIG_SYS_SDRAM_BASE 0x60000000
30 #define SDRAM_MAX_SIZE 0x80000000
40 "scriptaddr=0x60000000\0" \
41 "pxefile_addr_r=0x60100000\0" \
42 "fdt_addr_r=0x61f00000\0" \
[all …]
H A Dve8313.h33 #define CONFIG_SYS_IMMR 0xE0000000
35 #define CONFIG_SYS_MEMTEST_START 0x00001000
36 #define CONFIG_SYS_MEMTEST_END 0x07000000
48 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
63 /* 0x80840102 */
65 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
66 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
67 | (0 << TIMING_CFG0_WRT_SHIFT) \
74 /* 0x0e720802 */
83 /* 0x26256222 */
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dsun3x.h6 #define SUN3X_IOMMU 0x60000000
7 #define SUN3X_ENAREG 0x61000000
8 #define SUN3X_INTREG 0x61001400
9 #define SUN3X_DIAGREG 0x61001800
10 #define SUN3X_ZS1 0x62000000
11 #define SUN3X_ZS2 0x62002000
12 #define SUN3X_LANCE 0x65002000
13 #define SUN3X_EEPROM 0x64000000
14 #define SUN3X_IDPROM 0x640007d8
15 #define SUN3X_VIDEO_BASE 0x50000000
[all …]
H A Dsun3xprom.h18 #define SUN3X_IOMMU 0x60000000
19 #define SUN3X_ENAREG 0x61000000
20 #define SUN3X_INTREG 0x61001400
21 #define SUN3X_DIAGREG 0x61001800
22 #define SUN3X_ZS1 0x62000000
23 #define SUN3X_ZS2 0x62002000
24 #define SUN3X_LANCE 0x65002000
25 #define SUN3X_EEPROM 0x64000000
26 #define SUN3X_IDPROM 0x640007d8
27 #define SUN3X_VIDEO_BASE 0x50400000
[all …]
/openbmc/u-boot/configs/
H A Delgin-rv1108_defconfig3 CONFIG_SYS_TEXT_BASE=0x60000000
6 CONFIG_DEBUG_UART_BASE=0x10210000
28 CONFIG_FASTBOOT_BUF_ADDR=0x62000000
29 CONFIG_FASTBOOT_BUF_SIZE=0x08000000
31 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
54 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
55 CONFIG_USB_GADGET_PRODUCT_NUM=0x110a
H A Devb-rv1108_defconfig3 CONFIG_SYS_TEXT_BASE=0x60000000
6 CONFIG_DEBUG_UART_BASE=0x10210000
25 CONFIG_FASTBOOT_BUF_ADDR=0x62000000
26 CONFIG_FASTBOOT_BUF_SIZE=0x08000000
52 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
53 CONFIG_USB_GADGET_PRODUCT_NUM=0x110a
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dcortina,sl3516-crypto.yaml46 reg = <0x62000000 0x10000>;
/openbmc/linux/arch/arm/mach-davinci/
H A Dda8xx.h33 #define DA8XX_CP_INTC_BASE 0xfffee000
37 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
39 #define DA8XX_JTAG_ID_REG 0x18
40 #define DA8XX_HOST1CFG_REG 0x44
41 #define DA8XX_CHIPSIG_REG 0x174
42 #define DA8XX_CFGCHIP0_REG 0x17c
43 #define DA8XX_CFGCHIP1_REG 0x180
44 #define DA8XX_CFGCHIP2_REG 0x184
45 #define DA8XX_CFGCHIP3_REG 0x188
46 #define DA8XX_CFGCHIP4_REG 0x18c
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Ddavinci-nand.txt23 Can be in the range [0-3].
31 If not set equal to 0x08.
37 If not set equal to 0x10.
80 reg = <0x62000000 0x807ff
81 0x68000000 0x8000>;
83 ti,davinci-mask-ale = <0>;
84 ti,davinci-mask-cle = <0>;
85 ti,davinci-mask-chipsel = <0>;
92 reg = <0x180000 0x7e80000>;
/openbmc/linux/arch/powerpc/boot/dts/
H A Da4m072.dts27 ranges = <0 0xf0000000 0x0000c000>;
28 reg = <0xf0000000 0x00000100>;
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
33 fsl,init-ext-48mhz-en = <0x0>;
34 fsl,init-fd-enable = <0x01>;
35 fsl,init-fd-counters = <0x3333>;
44 reg = <0x2000 0x100>;
45 interrupts = <2 1 0>;
50 reg = <0x2200 0x100>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dv3-v360epc-pci.txt18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
/openbmc/qemu/hw/arm/
H A Drealview.c35 #define SMP_BOOT_ADDR 0xe0000000
36 #define SMP_BOOTREG_ADDR 0x10000030
54 0x33b,
55 0x33b,
56 0x769,
57 0x76d
68 qdev_connect_gpio_out(splitter, 0, out1); in split_irq_from_named()
70 qdev_connect_gpio_out_named(src, outname, 0, in split_irq_from_named()
71 qdev_get_gpio_in(splitter, 0)); in split_irq_from_named()
93 int is_mpcore = 0; in realview_init()
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dintegratorap.dts17 #size-cells = <0>;
19 cpu@0 {
28 reg = <0>;
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
[all …]
/openbmc/u-boot/board/armltd/integrator/
H A Dpci.c28 #define INTEGRATOR_BOOT_ROM_BASE 0x20000000
29 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
36 #define PHYS_PCI_MEM_BASE 0x40000000
37 #define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */
38 #define PHYS_PCI_CONFIG_BASE 0x61000000
39 #define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */
40 #define SZ_256M 0x10000000
44 * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor
47 * 0x40000000?
49 #define PCI_BUS_NONMEM_START 0x00000000
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8195-demo.dts38 pinctrl-0 = <&gpio_keys_pins>;
40 key-0 {
51 reg = <0 0x40000000 0x2 0x00000000>;
61 * +-----------------------+ 0x43e0_0000
63 * +-----------------------+ 0x43c0_0000
65 * + TZDRAM +--------------+ 0x4340_0000
67 * +-----------------------+ 0x4320_0000
71 reg = <0 0x43200000 0 0x00c00000>;
76 reg = <0 0x50000000 0 0x2900000>;
82 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
[all …]
/openbmc/linux/arch/arm/boot/dts/gemini/
H A Dgemini.dtsi23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h35 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
36 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
37 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
38 #define DAVINCI_UART0_BASE (0x01c20000)
39 #define DAVINCI_UART1_BASE (0x01c20400)
40 #define DAVINCI_TIMER3_BASE (0x01c20800)
41 #define DAVINCI_I2C_BASE (0x01c21000)
42 #define DAVINCI_TIMER0_BASE (0x01c21400)
43 #define DAVINCI_TIMER1_BASE (0x01c21800)
44 #define DAVINCI_WDOG_BASE (0x01c21c00)
[all …]
/openbmc/linux/drivers/video/fbdev/via/
H A Daccel.c19 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc; in viafb_set_bpp()
35 return 0; in viafb_set_bpp()
44 u32 ge_cmd = 0, tmp, i; in hw_bitblt_1()
54 ge_cmd |= 0x00008000; in hw_bitblt_1()
59 ge_cmd |= 0x00004000; in hw_bitblt_1()
67 case 0x00: /* blackness */ in hw_bitblt_1()
68 case 0x5A: /* pattern inversion */ in hw_bitblt_1()
69 case 0xF0: /* pattern copy */ in hw_bitblt_1()
70 case 0xFF: /* whiteness */ in hw_bitblt_1()
84 if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000) in hw_bitblt_1()
[all …]
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dsc9860.dtsi17 #size-cells = <0>;
54 reg = <0x0 0x530000>;
62 reg = <0x0 0x530001>;
70 reg = <0x0 0x530002>;
78 reg = <0x0 0x530003>;
86 reg = <0x0 0x530100>;
94 reg = <0x0 0x530101>;
102 reg = <0x0 0x530102>;
110 reg = <0x0 0x530103>;
125 arm,psci-suspend-param = <0x00010002>;
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]

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