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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dmstar,msc313e-timer.yaml10 - Daniel Palmer <daniel@0x0f.com>
42 reg = <0x6040 0x40>;
44 interrupts-extended = <&intc_fiq GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dtegra.h10 #define NV_PA_ARM_PERIPHBASE 0x50040000
11 #define NV_PA_PG_UP_BASE 0x60000000
12 #define NV_PA_TMRUS_BASE 0x60005010
13 #define NV_PA_CLK_RST_BASE 0x60006000
14 #define NV_PA_FLOW_BASE 0x60007000
15 #define NV_PA_GPIO_BASE 0x6000D000
16 #define NV_PA_EVP_BASE 0x6000F000
17 #define NV_PA_APB_MISC_BASE 0x70000000
18 #define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
19 #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
[all …]
/openbmc/linux/drivers/media/usb/gspca/gl860/
H A Dgl860-ov2640.c12 static u8 c61[] = {0x61}; /* expected */
13 static u8 c51[] = {0x51}; /* expected */
14 static u8 c50[] = {0x50}; /* expected */
15 static u8 c28[] = {0x28}; /* expected */
16 static u8 ca8[] = {0xa8}; /* expected */
27 {0x0000, 0x0000}, {0x0010, 0x0010}, {0x0008, 0x00c0}, {0x0001, 0x00c1},
28 {0x0001, 0x00c2}, {0x0020, 0x0006}, {0x006a, 0x000d},
29 {0x0050, 0x0000}, {0x0041, 0x0000}, {0x006a, 0x0007}, {0x0061, 0x0006},
30 {0x006a, 0x000d}, {0x0000, 0x00c0}, {0x0010, 0x0010}, {0x0001, 0x00c1},
31 {0x0041, 0x00c2}, {0x0004, 0x00d8}, {0x0012, 0x0004}, {0x0000, 0x0058},
[all …]
/openbmc/linux/drivers/staging/fbtft/
H A Dfb_ssd1289.c22 static unsigned int reg11 = 0x6040;
30 write_reg(par, 0x00, 0x0001); in init_display()
31 write_reg(par, 0x03, 0xA8A4); in init_display()
32 write_reg(par, 0x0C, 0x0000); in init_display()
33 write_reg(par, 0x0D, 0x080C); in init_display()
34 write_reg(par, 0x0E, 0x2B00); in init_display()
35 write_reg(par, 0x1E, 0x00B7); in init_display()
36 write_reg(par, 0x01, in init_display()
38 write_reg(par, 0x02, 0x0600); in init_display()
39 write_reg(par, 0x10, 0x0000); in init_display()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dcoredump.c19 {0x800, 0x810},
20 {0x820, 0x82C},
21 {0x830, 0x8F4},
22 {0x90C, 0x91C},
23 {0xA14, 0xA18},
24 {0xA84, 0xA94},
25 {0xAA8, 0xAD4},
26 {0xADC, 0xB40},
27 {0x1000, 0x10A4},
28 {0x10BC, 0x111C},
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/westmereex/
H A Dmemory.json4 "EventCode": "0x5",
7 "UMask": "0x2"
11 "EventCode": "0xB7",
13 "MSRIndex": "0x1A6",
14 "MSRValue": "0x6011",
16 "UMask": "0x1"
20 "EventCode": "0xB7",
22 "MSRIndex": "0x1A6",
23 "MSRValue": "0xF811",
25 "UMask": "0x1"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/nehalemex/
H A Dmemory.json4 "EventCode": "0xB7",
6 "MSRIndex": "0x1A6",
7 "MSRValue": "0x6011",
9 "UMask": "0x1"
13 "EventCode": "0xB7",
15 "MSRIndex": "0x1A6",
16 "MSRValue": "0xF811",
18 "UMask": "0x1"
22 "EventCode": "0xB7",
24 "MSRIndex": "0x1A6",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/nehalemep/
H A Dmemory.json4 "EventCode": "0xB7",
6 "MSRIndex": "0x1A6",
7 "MSRValue": "0x6011",
9 "UMask": "0x1"
13 "EventCode": "0xB7",
15 "MSRIndex": "0x1A6",
16 "MSRValue": "0xF811",
18 "UMask": "0x1"
22 "EventCode": "0xB7",
24 "MSRIndex": "0x1A6",
[all …]
/openbmc/linux/drivers/rtc/
H A Drtc-pm8xxx.c24 #define PM8xxx_RTC_ALARM_CLEAR BIT(0)
27 #define NUM_8_BIT_RTC_REGS 0x4
94 return 0; in pm8xxx_rtc_read_nvmem_offset()
105 if (rc < 0) { in pm8xxx_rtc_write_nvmem_offset()
110 return 0; in pm8xxx_rtc_write_nvmem_offset()
116 return 0; in pm8xxx_rtc_read_offset()
137 if (rc < 0) in pm8xxx_rtc_read_raw()
140 if (reg < value[0]) { in pm8xxx_rtc_read_raw()
149 return 0; in pm8xxx_rtc_read_raw()
168 return 0; in pm8xxx_rtc_update_offset()
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/westmereep-sp/
H A Dmemory.json4 "EventCode": "0xB7, 0xBB",
6 "MSRIndex": "0x1a6,0x1a7",
7 "MSRValue": "0x6011",
9 "UMask": "0x1"
13 "EventCode": "0xB7, 0xBB",
15 "MSRIndex": "0x1a6,0x1a7",
16 "MSRValue": "0xF811",
18 "UMask": "0x1"
22 "EventCode": "0xB7, 0xBB",
24 "MSRIndex": "0x1a6,0x1a7",
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_dbg.c13 * | Module Init and Probe | 0x0199 | |
14 * | Mailbox commands | 0x1206 | 0x11a5-0x11ff |
15 * | Device Discovery | 0x2134 | 0x2112-0x2115 |
16 * | | | 0x2127-0x2128 |
17 * | Queue Command and IO tracing | 0x3074 | 0x300b |
18 * | | | 0x3027-0x3028 |
19 * | | | 0x303d-0x3041 |
20 * | | | 0x302e,0x3033 |
21 * | | | 0x3036,0x3038 |
22 * | | | 0x303a |
[all …]
/openbmc/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_reg.h10 #define HNS_DEBUG_RING_IRQ_IDX 0
46 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100
47 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180
48 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184
49 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188
50 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C
51 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190
52 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194
53 #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300
54 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304
[all …]
/openbmc/linux/drivers/net/wireless/ti/wl12xx/
H A Dreg.h16 #define REGISTERS_BASE 0x00300000
17 #define DRPW_BASE 0x00310000
19 #define REGISTERS_DOWN_SIZE 0x00008800
20 #define REGISTERS_WORK_SIZE 0x0000b000
22 #define FW_STATUS_ADDR (0x14FC0 + 0xA000)
28 0 SOFT_RESET Soft Reset - When this bit is set,
38 #define WL12XX_SLV_SOFT_RESET (REGISTERS_BASE + 0x0000)
40 #define WL1271_SLV_REG_DATA (REGISTERS_BASE + 0x0008)
41 #define WL1271_SLV_REG_ADATA (REGISTERS_BASE + 0x000c)
42 #define WL1271_SLV_MEM_DATA (REGISTERS_BASE + 0x0018)
[all …]
/openbmc/linux/drivers/media/pci/cx88/
H A Dcx88-cards.c19 static unsigned int tuner[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
20 static unsigned int radio[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
21 static unsigned int card[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
43 } while (0)
60 .vmux = 0,
81 .vmux = 0,
82 .gpio0 = 0xff00, // internal decoder
85 .vmux = 0,
86 .gpio0 = 0xff01, // mono from tuner chip
90 .gpio0 = 0xff02,
[all …]
H A Dcx88-dvb.c71 } while (0)
84 sizes[0] = dev->ts_packet_size * dev->ts_packet_count; in queue_setup()
86 return 0; in queue_setup()
108 memset(risc, 0, sizeof(*risc)); in buffer_finish()
128 return 0; in start_streaming()
167 int ret = 0; in cx88_dvb_bus_ctrl()
184 dev->frontends.active_fe_id = 0; in cx88_dvb_bus_ctrl()
218 static const u8 clock_config[] = { CLOCK_CTL, 0x38, 0x39 }; in dvico_fusionhdtv_demod_init()
219 static const u8 reset[] = { RESET, 0x80 }; in dvico_fusionhdtv_demod_init()
220 static const u8 adc_ctl_1_cfg[] = { ADC_CTL_1, 0x40 }; in dvico_fusionhdtv_demod_init()
[all …]
/openbmc/u-boot/cmd/aspeed/nettest/
H A Dphy.c43 GPIO_WR(GPIO_RD(0x20) | RTK_DBG_GPIO, 0x20); in rtk_dbg_gpio_set()
50 GPIO_WR(GPIO_RD(0x20) & ~RTK_DBG_GPIO, 0x20); in rtk_dbg_gpio_clr()
57 GPIO_WR(GPIO_RD(0x24) | RTK_DBG_GPIO, 0x24); in rtk_dbg_gpio_init()
69 int timeout = 0; in phy_write()
89 writel(data, eng->run.mdio_base + 0x4); in phy_write()
109 printf("[Wr ]%02d: 0x%04x (%02d:%08x)\n", index, data, in phy_write()
112 PRINTF(FP_LOG, "[Wr ]%02d: 0x%04x (%02d:%08x)\n", index, in phy_write()
122 int timeout = 0; in phy_read()
124 if (index > 0x1f) { in phy_read()
125 printf("invalid PHY register index: 0x%02x\n", index); in phy_read()
[all …]
/openbmc/linux/drivers/net/ethernet/rdc/
H A Dr6040.c50 #define MCR0 0x00 /* Control register 0 */
51 #define MCR0_RCVEN 0x0002 /* Receive enable */
52 #define MCR0_PROMISC 0x0020 /* Promiscuous mode */
53 #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
54 #define MCR0_XMTEN 0x1000 /* Transmission enable */
55 #define MCR0_FD 0x8000 /* Full/Half duplex */
56 #define MCR1 0x04 /* Control register 1 */
57 #define MAC_RST 0x0001 /* Reset the MAC */
58 #define MBCR 0x08 /* Bus control */
59 #define MT_ICR 0x0C /* TX interrupt control */
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2.h28 #define MVPP2_XDP_PASS 0
29 #define MVPP2_XDP_DROPPED BIT(0)
34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
36 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
37 #define MVPP2_RX_FIFO_INIT_REG 0x64
38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))
39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
43 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
[all …]
/openbmc/linux/drivers/usb/serial/
H A Dftdi_sio_ids.h17 #define FTDI_VID 0x0403 /* Vendor Id */
22 #define FTDI_8U232AM_PID 0x6001 /* Similar device to SIO above */
23 #define FTDI_8U232AM_ALT_PID 0x6006 /* FTDI's alternate PID for above */
24 #define FTDI_8U2232C_PID 0x6010 /* Dual channel device */
25 #define FTDI_4232H_PID 0x6011 /* Quad channel hi-speed device */
26 #define FTDI_232H_PID 0x6014 /* Single channel hi-speed device */
27 #define FTDI_FTX_PID 0x6015 /* FT-X series (FT201X, FT230X, FT231X, etc) */
28 #define FTDI_FT2233HP_PID 0x6040 /* Dual channel hi-speed device with PD */
29 #define FTDI_FT4233HP_PID 0x6041 /* Quad channel hi-speed device with PD */
30 #define FTDI_FT2232HP_PID 0x6042 /* Dual channel hi-speed device with PD */
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dsid.h29 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
31 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
39 #define SI_MAX_BACKENDS_MASK 0xFF
40 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
42 #define SI_MAX_SIMDS_MASK 0x0FFF
43 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
45 #define SI_MAX_PIPES_MASK 0xFF
46 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
47 #define SI_MAX_LDS_NUM 0xFFFF
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dcamcc-sm8250.c36 { 249600000, 2000000000, 0 },
40 { 595200000UL, 3600000000UL, 0 },
44 .l = 0x3e,
45 .alpha = 0x8000,
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00002261,
48 .config_ctl_hi1_val = 0x329A699c,
49 .user_ctl_val = 0x00003100,
50 .user_ctl_hi_val = 0x00000805,
51 .user_ctl_hi1_val = 0x00000000,
[all …]
/openbmc/linux/Documentation/admin-guide/laptops/
H A Dthinkpad-acpi.rst152 (output in hex format: 0xAAAABBCC), where:
210 events. If a key is "masked" (bit set to 0 in the mask), the firmware
239 echo 0xffffffff > /proc/acpi/ibm/hotkey -- enable all hot keys
240 echo 0 > /proc/acpi/ibm/hotkey -- disable all possible hot keys
261 Returns 0.
268 to this value. This is always 0x80c, because those are
275 0: returns -EPERM
322 0 and 25 Hz. Polling is only carried out when strictly
336 attribute will read 0 if the switch is in the "radios
344 will read 0 if the ThinkPad is in normal mode, and
[all …]
/openbmc/linux/include/linux/
H A Dpci_ids.h15 #define PCI_CLASS_NOT_DEFINED 0x0000
16 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
18 #define PCI_BASE_CLASS_STORAGE 0x01
19 #define PCI_CLASS_STORAGE_SCSI 0x0100
20 #define PCI_CLASS_STORAGE_IDE 0x0101
21 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
22 #define PCI_CLASS_STORAGE_IPI 0x0103
23 #define PCI_CLASS_STORAGE_RAID 0x0104
24 #define PCI_CLASS_STORAGE_SATA 0x0106
25 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
[all …]

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