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/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,qcm2290.yaml90 reg = <0x01880000 0x60200>;
123 reg = <0x01900000 0x8200>;
132 reg = <0x04480000 0x80000>;
/openbmc/u-boot/drivers/video/
H A Di915_reg.h11 #define PORT_HOTPLUG_EN 0x61110
23 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
26 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
28 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
33 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
35 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
39 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
44 #define BLM_PIPE_A (0 << 29)
53 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
55 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dmme0_ctrl_regs.h22 #define mmMME0_CTRL_ARCH_STATUS 0x60000
24 #define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_S 0x60008
26 #define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_L 0x6000C
28 #define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_O 0x60010
30 #define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_S 0x60014
32 #define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_L 0x60018
34 #define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_O 0x6001C
36 #define mmMME0_CTRL_ARCH_HEADER_LOW 0x60020
38 #define mmMME0_CTRL_ARCH_HEADER_HIGH 0x60024
40 #define mmMME0_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x60028
[all …]
/openbmc/linux/drivers/interconnect/qcom/
H A Dqcm2290.c111 .qos.qos_port = 0,
113 .qos.prio_level = 0,
114 .qos.areq_prio = 0,
115 .mas_rpm_id = 0,
538 .qos.qos_port = 0,
666 .qos.prio_level = 0,
667 .qos.areq_prio = 0,
680 .slv_rpm_id = 0,
1189 .max_register = 0x80000,
1201 .qos_offset = 0x8000,
[all …]
/openbmc/linux/drivers/edac/
H A Dthunderx_edac.c54 int ret = 0; in decode_register()
74 #define L2C_CTL 0x87E080800000
75 #define L2C_CTL_DISIDXALIAS BIT(0)
77 #define PCI_DEVICE_ID_THUNDER_LMC 0xa022
79 #define LMC_FADR 0x20
80 #define LMC_FADR_FDIMM(x) ((x >> 37) & 0x1)
81 #define LMC_FADR_FBUNK(x) ((x >> 36) & 0x1)
82 #define LMC_FADR_FBANK(x) ((x >> 32) & 0xf)
83 #define LMC_FADR_FROW(x) ((x >> 14) & 0xffff)
84 #define LMC_FADR_FCOL(x) ((x >> 0) & 0x1fff)
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_8_0_offset.h29 // base address: 0x60000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_reg.h106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
119 #define GU_CNTL_PROTECTED _MMIO(0x10100C)
122 #define GU_CNTL _MMIO(0x101010)
125 #define GU_DEBUG _MMIO(0x101018)
128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
129 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
H A Dbnx2x_reg.h26 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
27 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
28 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
29 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
30 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
31 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
33 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
35 #define ATC_REG_ATC_INIT_DONE 0x1100bc
36 /* [RC 6] Interrupt register #0 read clear */
37 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
[all …]
/openbmc/linux/fs/unicode/
H A Dutf8data.c_shipped8 0,
9 0x10100,
10 0x20000,
11 0x20100,
12 0x30000,
13 0x30100,
14 0x30200,
15 0x40000,
16 0x40100,
17 0x50000,
[all …]