Home
last modified time | relevance | path

Searched +full:0 +full:x6000d000 (Results 1 – 14 of 14) sorted by relevance

/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dnvidia,tegra20-gpio.txt11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
16 bits[3:0] trigger type and level flags:
28 reg = < 0x6000d000 0x1000 >;
29 interrupts = < 0 32 0x04
30 0 33 0x04
31 0 34 0x04
32 0 35 0x04
33 0 55 0x04
34 0 87 0x04
35 0 89 0x04 >;
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dnvidia,tegra20-gpio.yaml37 to specify the GPIO polarity (0 = active high, 1 = active low).
50 bits[3:0] trigger type and level flags:
98 reg = <0x6000d000 0x1000>;
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dtegra.h10 #define NV_PA_ARM_PERIPHBASE 0x50040000
11 #define NV_PA_PG_UP_BASE 0x60000000
12 #define NV_PA_TMRUS_BASE 0x60005010
13 #define NV_PA_CLK_RST_BASE 0x60006000
14 #define NV_PA_FLOW_BASE 0x60007000
15 #define NV_PA_GPIO_BASE 0x6000D000
16 #define NV_PA_EVP_BASE 0x6000F000
17 #define NV_PA_APB_MISC_BASE 0x70000000
18 #define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
19 #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra20.dtsi14 reg = <0x50000000 0x00024000>;
24 ranges = <0x54000000 0x54000000 0x04000000>;
28 reg = <0x54040000 0x00040000>;
37 reg = <0x54080000 0x00040000>;
46 reg = <0x540c0000 0x00040000>;
55 reg = <0x54100000 0x00040000>;
64 reg = <0x54140000 0x00040000>;
73 reg = <0x54180000 0x00040000>;
81 reg = <0x54200000 0x00040000>;
89 nvidia,head = <0>;
[all …]
H A Dtegra114.dtsi15 reg = <0x50000000 0x00028000>;
25 ranges = <0x54000000 0x54000000 0x01000000>;
29 reg = <0x54140000 0x00040000>;
38 reg = <0x54180000 0x00040000>;
46 reg = <0x54200000 0x00040000>;
56 nvidia,head = <0>;
65 reg = <0x54240000 0x00040000>;
84 reg = <0x54280000 0x00040000>;
96 reg = <0x54300000 0x00040000>;
103 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
[all …]
H A Dtegra210.dtsi17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
18 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
19 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
26 interrupt-map-mask = <0 0 0 0>;
27 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
29 bus-range = <0x00 0xff>;
33 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
35 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
36 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
[all …]
H A Dtegra30.dtsi16 reg = <0x00003000 0x00000800 /* PADS registers */
17 0x00003800 0x00000200 /* AFI registers */
18 0x10000000 0x10000000>; /* configuration space */
25 interrupt-map-mask = <0 0 0 0>;
26 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
28 bus-range = <0x00 0xff>;
32 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
33 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
34 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
35 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
[all …]
H A Dtegra124.dtsi20 reg = <0x01003000 0x00000800 /* PADS registers */
21 0x01003800 0x00000800 /* AFI registers */
22 0x02000000 0x10000000>; /* configuration space */
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 bus-range = <0x00 0xff>;
36 ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000 /* port 0 configuration space */
37 0x82000000 0 0x01001000 0x01001000 0 0x00001000 /* port 1 configuration space */
38 0x81000000 0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
39 0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra114.dtsi17 reg = <0x80000000 0x0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x50000000 0x00028000>;
48 ranges = <0x54000000 0x54000000 0x01000000>;
52 reg = <0x54140000 0x00040000>;
63 reg = <0x54180000 0x00040000>;
73 reg = <0x54200000 0x00040000>;
83 nvidia,head = <0>;
[all …]
H A Dtegra20.dtsi17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc00>;
37 reg = <0x50000000 0x00024000>;
51 ranges = <0x54000000 0x54000000 0x04000000>;
55 reg = <0x54040000 0x00040000>;
67 reg = <0x54080000 0x00040000>;
79 reg = <0x540c0000 0x00040000>;
[all …]
H A Dtegra124.dtsi21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
39 bus-range = <0x00 0xff>;
43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
[all …]
H A Dtegra30.dtsi20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0 0 0>;
36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
38 bus-range = <0x00 0xff>;
42 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
43 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
44 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
H A Dtegra210.dtsi21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]