Lines Matching +full:0 +full:x6000d000

10 #define NV_PA_ARM_PERIPHBASE	0x50040000
11 #define NV_PA_PG_UP_BASE	0x60000000
12 #define NV_PA_TMRUS_BASE	0x60005010
13 #define NV_PA_CLK_RST_BASE	0x60006000
14 #define NV_PA_FLOW_BASE		0x60007000
15 #define NV_PA_GPIO_BASE		0x6000D000
16 #define NV_PA_EVP_BASE		0x6000F000
17 #define NV_PA_APB_MISC_BASE	0x70000000
18 #define NV_PA_APB_MISC_GP_BASE	(NV_PA_APB_MISC_BASE + 0x0800)
19 #define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)
20 #define NV_PA_APB_UARTB_BASE	(NV_PA_APB_MISC_BASE + 0x6040)
21 #define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
22 #define NV_PA_APB_UARTD_BASE	(NV_PA_APB_MISC_BASE + 0x6300)
23 #define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
24 #define NV_PA_NAND_BASE		(NV_PA_APB_MISC_BASE + 0x8000)
25 #define NV_PA_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
26 #define NV_PA_SLINK1_BASE	(NV_PA_APB_MISC_BASE + 0xD400)
27 #define NV_PA_SLINK2_BASE	(NV_PA_APB_MISC_BASE + 0xD600)
28 #define NV_PA_SLINK3_BASE	(NV_PA_APB_MISC_BASE + 0xD800)
29 #define NV_PA_SLINK4_BASE	(NV_PA_APB_MISC_BASE + 0xDA00)
30 #define NV_PA_SLINK5_BASE	(NV_PA_APB_MISC_BASE + 0xDC00)
31 #define NV_PA_SLINK6_BASE	(NV_PA_APB_MISC_BASE + 0xDE00)
32 #define TEGRA_DVC_BASE		(NV_PA_APB_MISC_BASE + 0xD000)
33 #define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
34 #define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
35 #define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
38 #define NV_PA_CSITE_BASE	0x70040000
40 #define NV_PA_CSITE_BASE	0x70800000
42 #define TEGRA_USB_ADDR_MASK	0xFFFFC000
45 #define LOW_LEVEL_SRAM_STACK	0x4000FFFC
46 #define EARLY_AVP_STACK		(NV_PA_SDRAM_BASE + 0x20000)
48 #define PG_UP_TAG_AVP		0xAAAAAAAA
56 #define NV_WB_RUN_ADDRESS	0x40020000
59 #define NVBOOTINFOTABLE_BOOTTYPE 0xC	/* Boot type in BIT in IRAM */
60 #define NVBOOTINFOTABLE_BCTSIZE	0x38	/* BCT size in BIT in IRAM */
61 #define NVBOOTINFOTABLE_BCTPTR	0x3C	/* BCT pointer in BIT in IRAM */
65 	SKU_ID_T20_7		= 0x7,
66 	SKU_ID_T20		= 0x8,
67 	SKU_ID_T25SE		= 0x14,
68 	SKU_ID_AP25		= 0x17,
69 	SKU_ID_T25		= 0x18,
70 	SKU_ID_AP25E		= 0x1b,
71 	SKU_ID_T25E		= 0x1c,
72 	SKU_ID_T33		= 0x80,
73 	SKU_ID_T30		= 0x81, /* Cardhu value */
74 	SKU_ID_TM30MQS_P_A3	= 0xb1,
75 	SKU_ID_T114_ENG		= 0x00, /* Dalmore value, unfused */
76 	SKU_ID_T114_1		= 0x01,
77 	SKU_ID_T124_ENG		= 0x00, /* Venice2 value, unfused */
78 	SKU_ID_T210_ENG		= 0x00, /* unfused value TBD */