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/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/fvp-base/
H A Doptee_spmc_maifest.dts23 spmc_id = <0x8000>;
24 maj_ver = <0x1>;
25 min_ver = <0x0>;
26 exec_state = <0x0>;
27 load_address = <0x0 0x6000000>;
28 entrypoint = <0x0 0x6000000>;
29 binary_size = <0x80000>;
40 tpm_event_log_addr = <0x0 0x0>;
41 tpm_event_log_size = <0x0>;
42 tpm_event_log_max_size = <0x0>;
[all …]
/openbmc/u-boot/arch/xtensa/dts/
H A Dxtfpga-flash-128m.dtsi7 reg = <0x00000000 0x08000000>;
10 partition@0x0 {
12 reg = <0x00000000 0x06000000>;
14 partition@0x6000000 {
16 reg = <0x06000000 0x00800000>;
18 partition@0x6800000 {
20 reg = <0x06800000 0x017e0000>;
22 partition@0x7fe0000 {
24 reg = <0x07fe0000 0x00020000>;
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Dopenbmc-flash-layout-128.dtsi8 u-boot@0 {
9 reg = <0x0 0xe0000>; // 896KB
14 reg = <0xe0000 0x20000>; // 128KB
19 reg = <0x100000 0x900000>; // 9MB
24 reg = <0xa00000 0x5600000>; // 86MB
29 reg = <0x6000000 0x2000000>; // 32MB
/openbmc/openbmc/meta-evb/meta-evb-arm/meta-evb-fvp-base/recipes-bsp/u-boot/files/
H A Dfvp.cfg3 CONFIG_SYS_BOOTM_LEN=0x6000000 # increase buffer size for decompression
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dst,st-hva.txt18 reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
/openbmc/u-boot/include/configs/
H A Dsmdkv310.h23 #define CONFIG_SYS_SDRAM_BASE 0x40000000
26 #define S5P_CHECK_SLEEP 0x00000BAD
27 #define S5P_CHECK_DIDLE 0xBAD00000
28 #define S5P_CHECK_LPA 0xABAD0000
31 #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000
38 #define COPY_BL2_FNPTR_ADDR 0x00002488
40 #define CONFIG_SPL_TEXT_BASE 0x02021410
42 #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
45 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
48 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
[all …]
H A Dorigen.h20 #define CONFIG_SYS_SDRAM_BASE 0x40000000
26 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
27 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
34 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
38 #define CONFIG_SYS_MONITOR_BASE 0x00000000
41 #define S5P_CHECK_SLEEP 0x00000BAD
42 #define S5P_CHECK_DIDLE 0xBAD00000
43 #define S5P_CHECK_LPA 0xABAD0000
46 #define COPY_BL2_FNPTR_ADDR 0x02020030
47 #define CONFIG_SPL_TEXT_BASE 0x02021410
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dcdns,usb3.yaml91 reg = <0x00 0x6000000 0x00 0x10000>,
92 <0x00 0x6010000 0x00 0x10000>,
93 <0x00 0x6020000 0x00 0x10000>;
H A Dti,j721e-usb.yaml45 If present, it restricts the controller to USB2.0 mode of
88 reg = <0x00 0x4104000 0x00 0x100>;
99 reg = <0x00 0x6000000 0x00 0x10000>,
100 <0x00 0x6010000 0x00 0x10000>,
101 <0x00 0x6020000 0x00 0x10000>;
103 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
105 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-lmu5000.dts20 reg = <0x20000000 0x4000000>;
28 main_clock: clock@0 {
43 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
48 reg = <0x3 0x0 0x800000>;
62 kernel@0 {
64 reg = <0x0 0x400000>;
69 reg = <0x400000 0x3C00000>;
74 reg = <0x4000000 0x2000000>;
79 reg = <0x6000000 0x2000000>;
107 pinctrl-0 = <&pinctrl_ssc0_tx>;
[all …]
/openbmc/u-boot/drivers/fastboot/
H A DKconfig28 default 0x82000000 if MX6SX || MX6SL || MX6UL || MX6SLL
29 default 0x81000000 if ARCH_OMAP2PLUS
30 default 0x42000000 if ARCH_SUNXI && !MACH_SUN9I
31 default 0x22000000 if ARCH_SUNXI && MACH_SUN9I
32 default 0x60800800 if ROCKCHIP_RK3036 || ROCKCHIP_RK3188 || \
34 default 0x800800 if ROCKCHIP_RK3288 || ROCKCHIP_RK3329 || \
36 default 0x280000 if ROCKCHIP_RK3368
37 default 0x100000 if ARCH_ZYNQMP
38 default 0 if SANDBOX
46 default 0x8000000 if ARCH_ROCKCHIP
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dstih410.dtsi18 cpu@0 {
19 st,syscfg = <&syscfg_core 0x8e0>;
20 st,syscfg-eng = <&syscfg_opp 0x4 0x0>;
35 opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
41 opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
46 opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
51 opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
60 reg = <0x08a6583c 0x8>;
65 #phy-cells = <0>;
66 st,syscfg = <&syscfg_core 0xf8 0xf4>;
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-linksys-rango.dts20 wan_amber@0 {
22 reg = <0x0>;
27 reg = <0x1>;
32 reg = <0x5>;
37 reg = <0x6>;
42 reg = <0x7>;
47 reg = <0x8>;
52 reg = <0x9>;
89 partition@0 {
91 reg = <0x0000000 0x200000>; /* 2MiB */
[all …]
/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_hwdb.c10 .model = 0x400,
11 .revision = 0x4652,
12 .product_id = 0x70001,
13 .customer_id = 0x100,
14 .eco_id = 0,
19 .nn_core_count = 0,
25 .buffer_size = 0,
27 .features = 0xa0e9e004,
28 .minor_features0 = 0xe1299fff,
29 .minor_features1 = 0xbe13b219,
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstih410.dtsi17 #phy-cells = <0>;
18 st,syscfg = <&syscfg_core 0xf8 0xf4>;
28 #phy-cells = <0>;
29 st,syscfg = <&syscfg_core 0xfc 0xf4>;
40 reg = <0x9a03c00 0x100>;
55 reg = <0x9a03e00 0x100>;
58 pinctrl-0 = <&pinctrl_usb0>;
72 reg = <0x9a83c00 0x100>;
87 reg = <0x9a83e00 0x100>;
90 pinctrl-0 = <&pinctrl_usb1>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/openbmc/linux/sound/soc/fsl/
H A Dfsl_rpmsg.c26 /* 192kHz/32bit/2ch/60s size is 0x574e00 */
27 #define LPA_LARGE_BUFFER_SIZE (0x6000000)
47 int ret = 0; in fsl_rpmsg_hw_params()
66 if (ret < 0) in fsl_rpmsg_hw_params()
95 return 0; in fsl_rpmsg_hw_free()
103 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, in fsl_rpmsg_startup()
248 0); in fsl_rpmsg_probe()
255 return 0; in fsl_rpmsg_probe()
290 return 0; in fsl_rpmsg_runtime_resume()
305 return 0; in fsl_rpmsg_runtime_suspend()
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-ldp.dts17 reg = <0x80000000 0x8000000>; /* 128 MB */
21 cpu@0 {
29 pinctrl-0 = <&gpio_key_pins>;
97 ranges = <0 0 0x30000000 0x1000000>, /* CS0 space, 16MB */
98 <1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */
100 nand@0,0 {
102 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
104 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
111 gpmc,sync-clk-ps = <0>;
112 gpmc,cs-on-ns = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dmba6ulx.dtsi36 pinctrl-0 = <&pinctrl_buttons>;
41 gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>;
119 gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>;
135 size = <0x6000000>;
151 pinctrl-0 = <&pinctrl_flexcan1>;
158 pinctrl-0 = <&pinctrl_flexcan2>;
170 pinctrl-0 = <&pinctrl_ecspi2>;
177 pinctrl-0 = <&pinctrl_enet1>;
189 pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>;
200 #size-cells = <0>;
[all …]
/openbmc/linux/arch/powerpc/platforms/pasemi/
H A Dsetup.c53 static int nmi_virq = 0;
63 out_le32(reset_reg, 0x6000000); in pas_restart()
70 void __iomem *pld_map = ioremap(0xf5000000,4096); in pas_shutdown()
72 out_8(pld_map+7,0x01); in pas_shutdown()
78 .start = 0x70,
79 .end = 0x71,
128 set_tb(timebase >> 32, timebase & 0xffffffff); in pas_take_timebase()
129 timebase = 0; in pas_take_timebase()
152 reset_reg = ioremap(0xfc101100, 4); in pas_setup_arch()
162 reg = 0; in pas_setup_mce_regs()
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dpgtable_64.h26 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
27 * The page copy blockops can use 0x6000000 to 0x8000000.
28 * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range.
29 * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range.
30 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
31 * The vmalloc area spans 0x100000000 to 0x200000000.
33 * we place them right before the OBP area from 0x10000000 to 0xf0000000.
34 * There is a single static kernel PMD which maps from 0x0 to address
35 * 0x400000000.
37 #define TLBTEMP_BASE _AC(0x0000000006000000,UL)
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/openbmc/linux/drivers/phy/freescale/
H A Dphy-fsl-lynx-28g.c15 #define LYNX_28G_PCC8 0x10a0
16 #define LYNX_28G_PCC8_SGMII 0x1
17 #define LYNX_28G_PCC8_SGMII_DIS 0x0
19 #define LYNX_28G_PCCC 0x10b0
20 #define LYNX_28G_PCCC_10GBASER 0x9
21 #define LYNX_28G_PCCC_USXGMII 0x1
22 #define LYNX_28G_PCCC_SXGMII_DIS 0x0
27 #define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
31 #define LYNX_28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
33 #define LYNX_28G_PLLnCR0_REFCLK_SEL_100MHZ 0x0
[all …]

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