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/openbmc/linux/drivers/power/supply/
H A Dmax17040_battery.c22 #define MAX17040_VCELL 0x02
23 #define MAX17040_SOC 0x04
24 #define MAX17040_MODE 0x06
25 #define MAX17040_VER 0x08
26 #define MAX17040_CONFIG 0x0C
27 #define MAX17040_STATUS 0x1A
28 #define MAX17040_CMD 0xFE
33 #define MAX17040_RCOMP_DEFAULT 0x9700
35 #define MAX17040_ATHD_MASK 0x3f
36 #define MAX17040_ALSC_MASK 0x40
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D07725 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
57 aio_write -P 10 0x200 0x200
62 off=0x1000
66 aio_write -P 10 $((off + 0x200)) 0x200
68 aio_write -P 11 $((off + 0x400)) 0x200
73 off=$((off + 0x1000))
79 aio_write -P 10 0x5000 0x200
81 aio_write -P 11 0x5200 0x200
82 aio_write -P 12 0x5400 0x200
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dlgdt3305.h16 LGDT3305_MPEG_PARALLEL = 0,
21 LGDT3305_TPCLK_RISING_EDGE = 0,
26 LGDT3305_TPCLK_GATED = 0,
31 LGDT3305_TP_VALID_LOW = 0,
36 LGDT3305 = 0,
48 u16 usref_8vsb; /* default: 0x32c4 */
49 u16 usref_qam64; /* default: 0x5400 */
50 u16 usref_qam256; /* default: 0x2a80 */
52 /* disable i2c repeater - 0:repeater enabled 1:repeater disabled */
55 /* spectral inversion - 0:disabled 1:enabled */
[all …]
H A Dstv6111.c37 { 2572, 0 },
73 { 1548, 0 },
109 { 4870, 0x3000 },
110 { 4850, 0x3C00 },
111 { 4800, 0x4500 },
112 { 4750, 0x4800 },
113 { 4700, 0x4B00 },
114 { 4650, 0x4D00 },
115 { 4600, 0x4F00 },
116 { 4550, 0x5100 },
[all …]
/openbmc/linux/drivers/bus/
H A Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Damlogic,aiu.yaml95 reg = <0x5400 0x2ac>;
/openbmc/u-boot/board/renesas/gose/
H A Dgose_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
44 u32 r0 = 0; in spl_init_sys()
46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys()
56 "orr %0, #0x1800 \n" in spl_init_sys()
[all …]
/openbmc/u-boot/board/renesas/koelsch/
H A Dkoelsch_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; in dbsc_wait()
39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
42 while (!(readl(dbsc3_1_base + reg) & BIT(0))) in dbsc_wait()
48 u32 r0 = 0; in spl_init_sys()
50 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
51 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
55 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
57 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
[all …]
/openbmc/u-boot/board/renesas/porter/
H A Dporter_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; in dbsc_wait()
39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
42 while (!(readl(dbsc3_1_base + reg) & BIT(0))) in dbsc_wait()
48 u32 r0 = 0; in spl_init_sys()
50 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
51 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
55 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
57 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
[all …]
/openbmc/qemu/hw/cpu/
H A Da15mpcore.c43 memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000); in a15mp_priv_initfn()
69 cpuobj = OBJECT(qemu_get_cpu(0)); in a15mp_priv_realize()
93 for (i = 0; i < s->num_cpu; i++) { in a15mp_priv_realize()
106 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { in a15mp_priv_realize()
119 * 0x0000-0x0fff -- reserved in a15mp_priv_realize()
120 * 0x1000-0x1fff -- GIC Distributor in a15mp_priv_realize()
121 * 0x2000-0x3fff -- GIC CPU interface in a15mp_priv_realize()
122 * 0x4000-0x4fff -- GIC virtual interface control for this CPU in a15mp_priv_realize()
123 * 0x5000-0x51ff -- GIC virtual interface control for CPU 0 in a15mp_priv_realize()
124 * 0x5200-0x53ff -- GIC virtual interface control for CPU 1 in a15mp_priv_realize()
[all …]
/openbmc/linux/drivers/media/usb/gspca/
H A Dw996Xcf.c53 Return 0 on success, -1 otherwise.
61 if (sd->gspca_dev.usb_err < 0) in w9968cf_write_fsb()
69 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 0, in w9968cf_write_fsb()
71 value, 0x06, sd->gspca_dev.usb_buf, 6, 500); in w9968cf_write_fsb()
72 if (ret < 0) { in w9968cf_write_fsb()
80 Return 0 on success, a negative number otherwise.
86 if (sd->gspca_dev.usb_err < 0) in w9968cf_write_sb()
95 usb_sndctrlpipe(sd->gspca_dev.dev, 0), in w9968cf_write_sb()
96 0, in w9968cf_write_sb()
98 value, 0x01, NULL, 0, 500); in w9968cf_write_sb()
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dtegra186_gpio.c66 return 0; in tegra186_gpio_set_out()
82 return 0; in tegra186_gpio_set_val()
95 ret = tegra186_gpio_set_val(dev, offset, value != 0); in tegra186_gpio_direction_output()
122 return tegra186_gpio_set_val(dev, offset, value != 0); in tegra186_gpio_set_value()
143 gpio = args->args[0]; in tegra186_gpio_xlate()
149 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; in tegra186_gpio_xlate()
151 return 0; in tegra186_gpio_xlate()
177 return 0; in tegra186_gpio_bind()
183 for (port = 0; port < ctlr_data->port_count; port++) { in tegra186_gpio_bind()
200 return 0; in tegra186_gpio_bind()
[all …]
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dnorthbridge.c30 stepping = result.eax & 0xf; in bridge_silicon_revision()
32 bridge_id &= 0xf0; in bridge_silicon_revision()
40 *base = 0; in get_pcie_bar()
41 *len = 0; in get_pcie_bar()
45 if (!(pciexbar_reg & (1 << 0))) in get_pcie_bar()
46 return 0; in get_pcie_bar()
49 case 0: /* 256MB */ in get_pcie_bar()
66 return 0; in get_pcie_bar()
74 debug("Adding PCIe config bar base=0x%08x size=0x%x\n", in add_fixed_resources()
82 writel(0xffffffff, DMIBAR_REG(0x1c4)); in northbridge_dmi_init()
[all …]
/openbmc/linux/arch/arm/boot/dts/amlogic/
H A Dmeson.dtsi28 reg = <0xc1100000 0x200000>;
31 ranges = <0x0 0xc1100000 0x200000>;
37 reg = <0x4000 0x400>;
44 reg = <0x5400 0x2ac>;
53 reg = <0x7c00 0x200>;
58 reg = <0x8100 0x8>;
63 reg = <0x84c0 0x18>;
71 reg = <0x84dc 0x18>;
78 reg = <0x8500 0x20>;
81 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/regulator/
H A Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/openbmc/u-boot/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7629.c18 PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
22 PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
26 PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
30 PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
34 PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
35 PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
36 PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
37 PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
38 PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
39 PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1),
[all …]
/openbmc/u-boot/drivers/usb/eth/
H A Dr8152_fw.c13 0x08, 0xe0, 0x40, 0xe0, 0x78, 0xe0, 0x85, 0xe0,
14 0x5d, 0xe1, 0xa1, 0xe1, 0xa3, 0xe1, 0xab, 0xe1,
15 0x31, 0xc3, 0x60, 0x72, 0xa0, 0x49, 0x10, 0xf0,
16 0xa4, 0x49, 0x0e, 0xf0, 0x2c, 0xc3, 0x62, 0x72,
17 0x26, 0x70, 0x80, 0x49, 0x05, 0xf0, 0x2f, 0x48,
18 0x62, 0x9a, 0x24, 0x70, 0x60, 0x98, 0x24, 0xc3,
19 0x60, 0x99, 0x23, 0xc3, 0x00, 0xbb, 0x2c, 0x75,
20 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13, 0x0a, 0xf0,
21 0x03, 0x13, 0x08, 0xf0, 0x02, 0x13, 0x06, 0xf0,
22 0x01, 0x13, 0x04, 0xf0, 0x08, 0x13, 0x02, 0xf0,
[all …]
/openbmc/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/openbmc/linux/sound/soc/codecs/
H A Drt1016.c31 {RT1016_VOL_CTRL_3, 0x8900},
32 {RT1016_ANA_CTRL_1, 0xa002},
33 {RT1016_ANA_CTRL_2, 0x0002},
34 {RT1016_CLOCK_4, 0x6700},
35 {RT1016_CLASSD_3, 0xdc55},
36 {RT1016_CLASSD_4, 0x376a},
37 {RT1016_CLASSD_5, 0x009f},
41 {0x00, 0x0000},
42 {0x01, 0x5400},
43 {0x02, 0x5506},
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2.h28 #define MVPP2_XDP_PASS 0
29 #define MVPP2_XDP_DROPPED BIT(0)
34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
36 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
37 #define MVPP2_RX_FIFO_INIT_REG 0x64
38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))
39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
43 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
[all …]
/openbmc/u-boot/board/intel/cherryhill/
H A Dcherryhill.c11 GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0,
12 VOLT_1_8, NA, NA, NA, 0, ENABLE, 2, SOUTHEAST),
15 GPIO_FAMILY_CONF("GPIO FAMILY TABLE END", NA, 0,
16 VOLT_1_8, NA, NA, NA, 0, DISABLE, 0, TERMINATOR),
22 NA, 29, NA, 0x4c38, NORTH),
25 NA, 27, NA, 0x4c28, NORTH),
28 NA, 20, NA, 0x4858, NORTH),
31 NA, 37, NA, 0x5018, NORTH),
34 NA, 42, NA, 0x5040, NORTH),
37 NA, 35, NA, 0x5008, NORTH),
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvid.h26 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
27 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */
30 #define KFD_VI_SDMA_QUEUE_OFFSET 0x80 /* not a register */
33 #define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c)
34 #define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c)
35 #define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c)
36 #define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c)
37 #define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c)
38 #define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c)
39 #define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c)
[all …]
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7629.c12 MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1)
15 PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
19 PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
23 PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
27 PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
31 PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
32 PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
33 PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
34 PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
35 PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
[all …]

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