Searched +full:0 +full:x53f80000 (Results 1 – 15 of 15) sorted by relevance
19 dummy 0109 reg = <0x53f80000 0x4000>;
19 ckih 0128 reg = <0x53f80000 0x4000>;
19 dummy 0175 reg = <0x53f80000 0x4000>;
60 #define FSL_IMX31_SECURE_ROM_ADDR 0x0000000061 #define FSL_IMX31_SECURE_ROM_SIZE 0x400062 #define FSL_IMX31_ROM_ADDR 0x0040400063 #define FSL_IMX31_ROM_SIZE 0x400064 #define FSL_IMX31_IRAM_ALIAS_ADDR 0x1000000065 #define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC000066 #define FSL_IMX31_IRAM_ADDR 0x1FFFC00067 #define FSL_IMX31_IRAM_SIZE 0x400068 #define FSL_IMX31_I2C1_ADDR 0x43F8000069 #define FSL_IMX31_I2C1_SIZE 0x4000[all …]
74 * 0x0000_0000 0x0000_3FFF 16 Kbytes ROM (36 Kbytes)75 * 0x0000_4000 0x0040_3FFF 4 Mbytes Reserved76 * 0x0040_4000 0x0040_8FFF 20 Kbytes ROM (36 Kbytes)77 * 0x0040_9000 0x0FFF_FFFF 252 Mbytes (minus 36 Kbytes) Reserved78 * 0x1000_0000 0x1FFF_FFFF 256 Mbytes Reserved79 * 0x2000_0000 0x2FFF_FFFF 256 Mbytes Reserved80 * 0x3000_0000 0x3FFF_FFFF 256 Mbytes Reserved81 * 0x4000_0000 0x43EF_FFFF 63 Mbytes Reserved82 * 0x43F0_0000 0x43F0_3FFF 16 Kbytes AIPS A control registers83 * 0x43F0_4000 0x43F0_7FFF 16 Kbytes ARM926 platform MAX[all …]
18 #define MX31_CCM_BASE_ADDR 0x53f8000019 #define MX31_GPT1_BASE_ADDR 0x53f9000022 #define MXC_CCM_CCMR 0x0023 #define MXC_CCM_PDR0 0x0424 #define MXC_CCM_PDR1 0x0825 #define MXC_CCM_MPCTL 0x1026 #define MXC_CCM_UPCTL 0x1427 #define MXC_CCM_SRPCTL 0x1828 #define MXC_CCM_CGR0 0x2029 #define MXC_CCM_CGR1 0x24[all …]
17 #define MX35_CCM_BASE_ADDR 0x53f8000018 #define MX35_GPT1_BASE_ADDR 0x53f9000021 #define MXC_CCM_PDR0 0x0422 #define MX35_CCM_PDR2 0x0c23 #define MX35_CCM_PDR3 0x1024 #define MX35_CCM_PDR4 0x1425 #define MX35_CCM_MPCTL 0x1c26 #define MX35_CCM_PPCTL 0x2027 #define MX35_CCM_CGR0 0x2c28 #define MX35_CCM_CGR1 0x30[all …]
16 #define IRAM_BASE_ADDR 0x10000000 /* internal ram */17 #define IRAM_SIZE 0x00020000 /* 128 KB */19 #define LOW_LEVEL_SRAM_STACK 0x1001E00024 #define AIPS1_BASE_ADDR 0x43F0000026 #define MAX_BASE_ADDR 0x43F0400027 #define EVTMON_BASE_ADDR 0x43F0800028 #define CLKCTL_BASE_ADDR 0x43F0C00029 #define I2C1_BASE_ADDR 0x43F8000030 #define I2C3_BASE_ADDR 0x43F8400031 #define ATA_BASE_ADDR 0x43F8C000[all …]
35 #size-cells = <0>;37 cpu@0 {40 reg = <0>;48 reg = <0x68000000 0x100000>;60 reg = <0x1fffc000 0x4000>;63 ranges = <0 0x1fffc000 0x4000>;70 reg = <0x43f00000 0x100000>;75 reg = <0x43f80000 0x4000>;79 #size-cells = <0>;85 reg = <0x43f84000 0x4000>;[all …]
39 #size-cells = <0>;41 cpu@0 {44 reg = <0>;52 reg = <0x68000000 0x10000000>;64 reg = <0x30000000 0x1000>;73 reg = <0x43f00000 0x100000>;78 #size-cells = <0>;80 reg = <0x43f80000 0x4000>;89 #size-cells = <0>;91 reg = <0x43f84000 0x4000>;[all …]
48 #size-cells = <0>;49 cpu@0 {52 reg = <0x0>;60 reg = <0x0fffc000 0x4000>;66 #clock-cells = <0>;72 #clock-cells = <0>;78 #clock-cells = <0>;79 clock-frequency = <0>;84 #clock-cells = <0>;89 usbphy0: usbphy-0 {[all …]
47 #size-cells = <0>;49 cpu@0 {52 reg = <0>;60 reg = <0x68000000 0x8000000>;66 #clock-cells = <0>;82 reg = <0x43f00000 0x100000>;87 reg = <0x43f00000 0x4000>;92 #size-cells = <0>;94 reg = <0x43f80000 0x4000>;103 #size-cells = <0>;[all …]
51 #size-cells = <0>;52 cpu0: cpu@0 {55 reg = <0x0>;84 reg = <0x0fffc000 0x4000>;90 #clock-cells = <0>;96 #clock-cells = <0>;102 #clock-cells = <0>;103 clock-frequency = <0>;108 #clock-cells = <0>;119 usbphy0: usbphy-0 {[all …]
27 u32 cgr0; /* Clock Gating Control 0 */33 u32 dcvr0; /* DPTC Comparator Value 0 */37 u32 ltr0; /* Load Tracking 0 */41 u32 ltbr0; /* Load Tracking Buffer 0 */43 u32 pcmr0; /* Power Management Control 0 */47 u32 lpimr0; /* Low Power Interrupt Mask 0 */53 u32 ctl0; /* control 0 */54 u32 cfg0; /* configuration 0 */104 u32 res1[0x1f1];106 u32 fuse_regs[0x20];[all …]
70 u32 res[0x1f1];72 u32 fuse_regs[0x20];73 u32 fuse_rsvd[0xe0];100 #define IOMUX_PADNUM_MASK 0x1ff107 PAD_CTL_NOLOOPBACK = 0x0 << 9,108 PAD_CTL_LOOPBACK = 0x1 << 9,109 PAD_CTL_PKE_NONE = 0x0 << 8,110 PAD_CTL_PKE_ENABLE = 0x1 << 8,111 PAD_CTL_PUE_KEEPER = 0x0 << 7,112 PAD_CTL_PUE_PUD = 0x1 << 7,[all …]