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/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dst,stm32-thermal.yaml30 const: 0
48 reg = <0x50028000 0x100>;
51 #thermal-sensor-cells = <0>;
57 polling-delay-passive = <0>;
58 polling-delay = <0>;
64 hysteresis = <0>;
70 hysteresis = <0>;
/openbmc/u-boot/arch/arm/include/asm/arch-mx25/
H A Dimx-regs.h27 u32 cgr0; /* Clock Gating Control 0 */
33 u32 dcvr0; /* DPTC Comparator Value 0 */
37 u32 ltr0; /* Load Tracking 0 */
41 u32 ltbr0; /* Load Tracking Buffer 0 */
43 u32 pcmr0; /* Power Management Control 0 */
47 u32 lpimr0; /* Low Power Interrupt Mask 0 */
53 u32 ctl0; /* control 0 */
54 u32 cfg0; /* configuration 0 */
104 u32 res1[0x1f1];
106 u32 fuse_regs[0x20];
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp151.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
82 #clock-cells = <0>;
[all …]
/openbmc/qemu/hw/arm/
H A Darmsse.c54 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */
85 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
86 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
87 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
88 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
89 DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
98 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
99 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
100 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
103 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
[all …]