Lines Matching +full:0 +full:x50028000
54 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */
85 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
86 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
87 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
88 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
89 DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
98 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
99 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
100 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
103 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
104 DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
115 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
116 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
117 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
118 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
119 DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
127 .index = 0,
128 .addr = 0x40000000,
129 .ppc = 0,
130 .ppc_port = 0,
137 .addr = 0x40001000,
138 .ppc = 0,
146 .addr = 0x4002f000,
148 .ppc_port = 0,
155 .index = 0,
156 .addr = 0x40002000,
157 .ppc = 0,
164 .index = 0,
165 .addr = 0x5002e000,
174 .addr = 0x40081000,
182 .addr = 0x50081000,
189 .index = 0,
190 .addr = 0x40020000,
197 .index = 0,
198 .addr = 0x50021000,
211 .index = 0,
212 .addr = 0x40000000,
213 .ppc = 0,
214 .ppc_port = 0,
221 .addr = 0x40001000,
222 .ppc = 0,
230 .addr = 0x4002f000,
232 .ppc_port = 0,
239 .index = 0,
240 .addr = 0x40002000,
241 .ppc = 0,
248 .index = 0,
249 .addr = 0x5002e000,
258 .addr = 0x40081000,
266 .addr = 0x50081000,
273 .index = 0,
274 .addr = 0x40020000,
281 .index = 0,
282 .addr = 0x50021000,
289 .index = 0,
290 .addr = 0x50023000,
291 .size = 0x1000,
299 .addr = 0x50025000,
300 .size = 0x1000,
308 .addr = 0x50029000,
309 .size = 0x1000,
317 .addr = 0x5002a000,
318 .size = 0x1000,
326 .addr = 0x5002b000,
327 .size = 0x1000,
335 .addr = 0x5002c000,
336 .size = 0x1000,
344 .addr = 0x5002d000,
345 .size = 0x1000,
353 .addr = 0x50022000,
354 .size = 0x1000,
367 .index = 0,
368 .addr = 0x48000000,
369 .ppc = 0,
370 .ppc_port = 0,
377 .addr = 0x48001000,
378 .ppc = 0,
386 .addr = 0x48002000,
387 .ppc = 0,
395 .addr = 0x48003000,
396 .ppc = 0,
403 .index = 0,
404 .addr = 0x4802f000,
406 .ppc_port = 0,
413 .index = 0,
414 .addr = 0x4802e000,
422 .index = 0,
423 .addr = 0x48040000,
424 .size = 0x2000,
431 .index = 0,
432 .addr = 0x48020000,
439 .index = 0,
440 .addr = 0x58021000,
448 .addr = 0x58022000,
449 .size = 0x1000,
457 .addr = 0x50023000,
458 .size = 0x1000,
466 .addr = 0x50028000,
467 .size = 0x1000,
475 .addr = 0x50029000,
476 .size = 0x1000,
487 [0 ... 5] = true,
501 [0 ... 5] = true,
518 .sram_bank_base = 0x20000000,
520 .sys_version = 0x41743,
521 .iidr = 0,
522 .cpuwait_rst = 0,
539 .sram_bank_base = 0x20000000,
541 .sys_version = 0x22041743,
542 .iidr = 0,
560 .sram_bank_base = 0x21000000,
562 .sys_version = 0x7e00043b,
563 .iidr = 0x74a0043b,
564 .cpuwait_rst = 0,
585 sys_config = 0; in armsse_sys_config_value()
586 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); in armsse_sys_config_value()
590 sys_config = 0; in armsse_sys_config_value()
591 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); in armsse_sys_config_value()
601 sys_config = 0; in armsse_sys_config_value()
602 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); in armsse_sys_config_value()
675 qdev_connect_gpio_out(dev_splitter, 0, in armsse_forward_ppc()
677 name, 0)); in armsse_forward_ppc()
680 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); in armsse_forward_ppc()
711 s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL, 0); in armsse_init()
712 s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0); in armsse_init()
716 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
736 if (i > 0) { in armsse_init()
739 name, &s->container, 0, UINT64_MAX); in armsse_init()
752 assert(devinfo->index == 0); in armsse_init()
766 assert(devinfo->index == 0); in armsse_init()
770 assert(devinfo->index == 0); in armsse_init()
785 for (i = 0; i < ARRAY_SIZE(s->apb_ppc); i++) { in armsse_init()
790 for (i = 0; i < info->sram_banks; i++) { in armsse_init()
798 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { in armsse_init()
807 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); in armsse_init()
811 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
820 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
829 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
838 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
856 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { in armsse_init()
864 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { in armsse_init()
902 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); in armsse_get_common_irq_in()
905 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); in armsse_get_common_irq_in()
959 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS in armsse_realize()
975 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff in armsse_realize()
976 * 0x20000000..0x2007ffff 32KB FPGA block RAM in armsse_realize()
977 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff in armsse_realize()
978 * 0x40000000..0x4000ffff base peripheral region 1 in armsse_realize()
979 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) in armsse_realize()
980 * 0x40020000..0x4002ffff system control element peripherals in armsse_realize()
981 * 0x40080000..0x400fffff base peripheral region 2 in armsse_realize()
982 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff in armsse_realize()
985 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); in armsse_realize()
987 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1047 if (i > 0) { in armsse_realize()
1048 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, in armsse_realize()
1051 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, in armsse_realize()
1072 for (j = 0; j < s->exp_numirq; j++) { in armsse_realize()
1075 if (i == 0) { in armsse_realize()
1088 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { in armsse_realize()
1101 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { in armsse_realize()
1113 0x10000000, 0x10000000, 0x00000000); in armsse_realize()
1115 "alias 2", 0x30000000, 0x10000000, 0x20000000); in armsse_realize()
1116 /* The 0x50000000..0x5fffffff region is not a pure alias: it has in armsse_realize()
1123 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1125 "alias 3", 0x50000000, 0x10000000, 0x40000000); in armsse_realize()
1136 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); in armsse_realize()
1137 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); in armsse_realize()
1140 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); in armsse_realize()
1154 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, in armsse_realize()
1155 qdev_get_gpio_in(dev_splitter, 0)); in armsse_realize()
1158 for (i = 0; i < info->sram_banks; i++) { in armsse_realize()
1180 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, in armsse_realize()
1181 sysbus_mmio_get_region(sbd_mpc, 0)); in armsse_realize()
1193 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, in armsse_realize()
1204 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, in armsse_realize()
1205 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); in armsse_realize()
1220 memory_region_add_subregion(&s->container, 0x58100000, in armsse_realize()
1221 sysbus_mmio_get_region(sbd, 0)); in armsse_realize()
1222 memory_region_add_subregion(&s->container, 0x48101000, in armsse_realize()
1227 /* The SSE-300 has an ITCM at 0x0000_0000 and a DTCM at 0x2000_0000 */ in armsse_realize()
1236 memory_region_add_subregion(&s->container, 0x00000000, &s->itcm); in armsse_realize()
1237 memory_region_add_subregion(&s->container, 0x20000000, &s->dtcm); in armsse_realize()
1241 * 0x40000000: timer0 in armsse_realize()
1242 * 0x40001000: timer1 in armsse_realize()
1243 * 0x40002000: dual timer in armsse_realize()
1244 * 0x40003000: MHU0 (SSE-200 only) in armsse_realize()
1245 * 0x40004000: MHU1 (SSE-200 only) in armsse_realize()
1262 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1270 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1280 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1289 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1305 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1321 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1330 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1339 case 0 ... NUM_SSE_IRQS - 1: in armsse_realize()
1352 sysbus_connect_irq(sbd, 0, irq); in armsse_realize()
1382 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { in armsse_realize()
1391 mr = sysbus_mmio_get_region(mhu_sbd, 0); in armsse_realize()
1392 object_property_set_link(OBJECT(&s->apb_ppc[0]), port, OBJECT(mr), in armsse_realize()
1398 * MHU 0 irq line 0 -> CPU 0 IRQ 6 in armsse_realize()
1399 * MHU 0 irq line 1 -> CPU 1 IRQ 6 in armsse_realize()
1400 * MHU 1 irq line 0 -> CPU 0 IRQ 7 in armsse_realize()
1403 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { in armsse_realize()
1412 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[0]), errp)) { in armsse_realize()
1416 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc[0]); in armsse_realize()
1417 dev_apb_ppc0 = DEVICE(&s->apb_ppc[0]); in armsse_realize()
1421 memory_region_add_subregion(&s->container, 0x40003000, mr); in armsse_realize()
1423 memory_region_add_subregion(&s->container, 0x40004000, mr); in armsse_realize()
1425 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { in armsse_realize()
1433 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, in armsse_realize()
1435 "irq_enable", 0)); in armsse_realize()
1436 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, in armsse_realize()
1438 "irq_clear", 0)); in armsse_realize()
1439 qdev_connect_gpio_out(dev_splitter, 0, in armsse_realize()
1441 "cfg_sec_resp", 0)); in armsse_realize()
1454 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, in armsse_realize()
1458 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): in armsse_realize()
1460 * 0x50010000: L1 icache control registers in armsse_realize()
1461 * 0x50011000: CPUSECCTRL (CPU local security control registers) in armsse_realize()
1462 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block in armsse_realize()
1464 * 0x40012000 and 0x50012000: CPU_PWRCTRL register block in armsse_realize()
1467 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1472 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); in armsse_realize()
1477 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); in armsse_realize()
1478 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); in armsse_realize()
1482 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1487 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); in armsse_realize()
1492 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); in armsse_realize()
1493 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); in armsse_realize()
1497 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1504 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); in armsse_realize()
1505 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); in armsse_realize()
1509 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1515 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), 0); in armsse_realize()
1516 memory_region_add_subregion(&s->cpu_container[i], 0x40012000, mr); in armsse_realize()
1525 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, in armsse_realize()
1527 "cfg_nonsec", 0)); in armsse_realize()
1528 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, in armsse_realize()
1530 "cfg_ap", 0)); in armsse_realize()
1531 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, in armsse_realize()
1533 "irq_enable", 0)); in armsse_realize()
1534 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, in armsse_realize()
1536 "irq_clear", 0)); in armsse_realize()
1539 "cfg_sec_resp", 0)); in armsse_realize()
1558 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { in armsse_realize()
1569 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { in armsse_realize()
1576 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { in armsse_realize()
1590 qdev_connect_gpio_out(devs, 0, in armsse_realize()
1591 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); in armsse_realize()
1594 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, in armsse_realize()
1595 qdev_get_gpio_in(devs, 0)); in armsse_realize()
1600 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { in armsse_realize()
1614 s->mpcexp_status_in[i] = qdev_get_gpio_in(devs, 0); in armsse_realize()
1615 qdev_connect_gpio_out(devs, 0, in armsse_realize()
1621 "irq", 0, in armsse_realize()
1622 qdev_get_gpio_in(devs, 0)); in armsse_realize()
1623 qdev_connect_gpio_out(devs, 0, in armsse_realize()
1644 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, in armsse_realize()
1669 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ in armsse_idau_check()
1670 *exempt = (address & 0xeff00000) == 0xe0000000; in armsse_idau_check()
1690 s->nsccfg = 0; in armsse_reset()
1727 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { in armsse_register_types()