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/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dqcom,llcc.yaml162 reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,
163 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
164 <0 0x01300000 0 0x50000>;
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_hfi.c34 return 0; in a6xx_hfi_queue_read()
52 for (i = 0; i < HFI_HEADER_SIZE(hdr); i++) { in a6xx_hfi_queue_read()
82 for (i = 0; i < dwords; i++) { in a6xx_hfi_queue_write()
90 queue->data[index] = 0xfafafafa; in a6xx_hfi_queue_write()
96 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
97 return 0; in a6xx_hfi_queue_write()
165 return 0; in a6xx_hfi_wait_for_ack()
176 seqnum = atomic_inc_return(&queue->seqnum) % 0xfff; in a6xx_hfi_send_msg()
194 struct a6xx_hfi_msg_gmu_init_cmd msg = { 0 }; in a6xx_hfi_send_gmu_init()
201 NULL, 0); in a6xx_hfi_send_gmu_init()
[all …]
/openbmc/u-boot/doc/SPI/
H A DREADME.ti_qspi_dra_test11 U-Boot# mmc dev 0
13 U-Boot# fatload mmc 0 0x82000000 MLO
16 U-Boot# fatload mmc 0 0x83000000 u-boot.img
23 U-Boot# sf probe 0
25 U-Boot# sf erase 0 0x10000
26 SF: 65536 bytes @ 0x0 Erased: OK
27 U-Boot# sf erase 0x20000 0x10000
28 SF: 65536 bytes @ 0x20000 Erased: OK
29 U-Boot# sf erase 0x30000 0x10000
30 SF: 65536 bytes @ 0x30000 Erased: OK
[all …]
/openbmc/u-boot/doc/device-tree-bindings/firmware/
H A Dnvidia,tegra186-bpmp.txt76 reg = <0x0 0x30000000 0x0 0x50000>;
79 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
83 reg = <0x0 0x4e000 0x0 0x1000>;
88 reg = <0x0 0x4f000 0x0 0x1000>;
/openbmc/qemu/tests/qemu-iotests/
H A D274.out2 wrote 2097152/2097152 bytes at offset 0
6 read 1048576/1048576 bytes at offset 0
13 1048576/1048576 bytes allocated at offset 0 bytes
16 0/1048576 bytes allocated at offset 0 bytes
17 0/0 bytes allocated at offset 1 MiB
19 0/1048576 bytes allocated at offset 0 bytes
20 0/1048576 bytes allocated at offset 1 MiB
23 [{ "start": 0, "length": 2097152, "depth": 0, "present": true, "zero": false, "data": true, "compre…
26 0 0x200000 0x50000 TEST_DIR/PID-base
28 [{ "start": 0, "length": 1048576, "depth": 1, "present": true, "zero": false, "data": true, "compre…
[all …]
H A D112.out33 wrote 512/512 bytes at offset 0
36 Leaked cluster 6 refcount=1 reference=0
45 wrote 512/512 bytes at offset 0
48 Leaked cluster 7 refcount=1 reference=0
57 wrote 65536/65536 bytes at offset 0
67 wrote 512/512 bytes at offset 0
69 wrote 512/512 bytes at offset 0
76 wrote 512/512 bytes at offset 0
80 Leaked cluster 6 refcount=1 reference=0
111 wrote 16777216/16777216 bytes at offset 0
[all …]
H A D292.out4 ### Fill the backing image with data (0x11)
5 wrote 1048576/1048576 bytes at offset 0
9 ### Fill the top image with data (0x22)
10 wrote 1048576/1048576 bytes at offset 0
17 read 532480/532480 bytes at offset 0
23 0 0x8dc00 0x50000 TEST_DIR/t.qcow2
/openbmc/linux/arch/mips/boot/dts/ralink/
H A Drt2880_eval.dts10 memory@0 {
12 reg = <0x8000000 0x2000000>;
21 reg = <0x1f000000 0x400000>;
28 partition@0 {
30 reg = <0x0 0x30000>;
35 reg = <0x30000 0x10000>;
40 reg = <0x40000 0x10000>;
45 reg = <0x50000 0x3b0000>;
H A Drt3052_eval.dts10 memory@0 {
12 reg = <0x0 0x2000000>;
21 reg = <0x1f000000 0x800000>;
28 partition@0 {
30 reg = <0x0 0x30000>;
35 reg = <0x30000 0x10000>;
40 reg = <0x40000 0x10000>;
45 reg = <0x50000 0x7b0000>;
H A Dmt7621-gnubee-gb-pc1.dts13 memory@0 {
15 reg = <0x00000000 0x1c000000>,
16 <0x20000000 0x04000000>;
57 flash@0 {
61 reg = <0>;
65 partition@0 {
67 reg = <0x0 0x30000>;
73 reg = <0x30000 0x10000>;
79 reg = <0x40000 0x10000>;
85 reg = <0x50000 0x1fb0000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml147 reg = <0x03c00000 0xa0000>;
155 reg = <0x30000000 0x50000>;
158 ranges = <0x0 0x30000000 0x50000>;
161 reg = <0x4e000 0x1000>;
167 reg = <0x4f000 0x1000>;
191 #size-cells = <0>;
/openbmc/linux/drivers/crypto/
H A Dgeode-aes.h9 #define AES_MODE_ECB 0
12 #define AES_DIR_DECRYPT 0
15 #define AES_FLAGS_HIDDENKEY (1 << 0)
19 #define AES_CTRLA_REG 0x0000
21 #define AES_CTRL_START 0x01
22 #define AES_CTRL_DECRYPT 0x00
23 #define AES_CTRL_ENCRYPT 0x02
24 #define AES_CTRL_WRKEY 0x04
25 #define AES_CTRL_DCA 0x08
26 #define AES_CTRL_SCA 0x10
[all …]
/openbmc/linux/arch/arm/mach-orion5x/
H A Dorion5x.h36 #define ORION5X_REGS_PHYS_BASE 0xf1000000
37 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000)
40 #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
41 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000
44 #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
45 #define ORION5X_PCI_IO_BUS_BASE 0x00010000
48 #define ORION5X_SRAM_PHYS_BASE (0xf2200000)
52 #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
53 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
56 #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
[all …]
/openbmc/linux/arch/arm/mach-mmp/
H A Daddr-map.h15 #define APB_PHYS_BASE 0xd4000000
16 #define APB_VIRT_BASE IOMEM(0xfe000000)
17 #define APB_PHYS_SIZE 0x00200000
19 #define AXI_PHYS_BASE 0xd4200000
20 #define AXI_VIRT_BASE IOMEM(0xfe200000)
21 #define AXI_PHYS_SIZE 0x00200000
23 #define PGU_PHYS_BASE 0xe0000000
24 #define PGU_VIRT_BASE IOMEM(0xfe400000)
25 #define PGU_PHYS_SIZE 0x00100000
27 /* Static Memory Controller - Chip Select 0 and 1 */
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear600-evb.dts17 reg = <0 0x10000000>;
55 reg = <0xf8000000 0x800000>;
63 partition@0 {
65 reg = <0x0 0x10000>;
69 reg = <0x10000 0x50000>;
73 reg = <0x60000 0x10000>;
77 reg = <0x70000 0x10000>;
81 reg = <0x80000 0x310000>;
85 reg = <0x390000 0x0>;
/openbmc/u-boot/arch/arm/mach-orion5x/include/mach/
H A Dorion5x.h22 #define ORION5X_DRAM_BASE (ORION5X_REGISTER(0x01500))
23 #define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000))
24 #define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000))
25 #define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))
26 #define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000))
27 #define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100))
28 #define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000))
29 #define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100))
30 #define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300))
31 #define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000))
[all …]
/openbmc/u-boot/board/renesas/ebisu/
H A Debisu.c35 return 0; in board_early_init_f()
41 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; in board_init()
43 return 0; in board_init()
48 if (fdtdec_setup_mem_size_base() != 0) in dram_init()
51 return 0; in dram_init()
58 return 0; in dram_init_banksize()
61 #define RST_BASE 0xE6160000
62 #define RST_CA57RESCNT (RST_BASE + 0x40)
63 #define RST_CA53RESCNT (RST_BASE + 0x44)
64 #define RST_RSTOUTCR (RST_BASE + 0x58)
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dqoriq-bman-portals.dtsi14 bman-portal@0 {
20 reg = <0x0 0x4000>, <0x4000000 0x4000>;
26 reg = <0x10000 0x4000>, <0x4010000 0x4000>;
32 reg = <0x20000 0x4000>, <0x4020000 0x4000>;
38 reg = <0x30000 0x4000>, <0x4030000 0x4000>;
44 reg = <0x40000 0x4000>, <0x4040000 0x4000>;
50 reg = <0x50000 0x4000>, <0x4050000 0x4000>;
56 reg = <0x60000 0x4000>, <0x4060000 0x4000>;
62 reg = <0x70000 0x4000>, <0x4070000 0x4000>;
68 reg = <0x80000 0x4000>, <0x4080000 0x4000>;
[all …]
H A Dqoriq-qman-portals.dtsi14 qportal0: qman-portal@0 {
20 reg = <0x0 0x4000>, <0x4000000 0x4000>;
22 cell-index = <0>;
27 reg = <0x10000 0x4000>, <0x4010000 0x4000>;
34 reg = <0x20000 0x4000>, <0x4020000 0x4000>;
41 reg = <0x30000 0x4000>, <0x4030000 0x4000>;
48 reg = <0x40000 0x4000>, <0x4040000 0x4000>;
55 reg = <0x50000 0x4000>, <0x4050000 0x4000>;
62 reg = <0x60000 0x4000>, <0x4060000 0x4000>;
69 reg = <0x70000 0x4000>, <0x4070000 0x4000>;
[all …]
/openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dsoc.h16 #define INTREG_BASE 0xd0000000
18 #define KW_OFFSET_REG (INTREG_BASE + 0x20080)
21 #define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
22 #define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
24 #define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500))
25 #define KW_TWSI_BASE (KW_REGISTER(0x11000))
26 #define KW_UART0_BASE (KW_REGISTER(0x12000))
27 #define KW_UART1_BASE (KW_REGISTER(0x12100))
28 #define KW_MPP_BASE (KW_REGISTER(0x10000))
29 #define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100))
[all …]
/openbmc/u-boot/board/renesas/ulcb/
H A Dulcb.c42 return 0; in board_early_init_f()
46 #define HSUSB_REG_LPSTS 0xE6590102
48 #define HSUSB_REG_UGCTRL2 0xE6590184
49 #define HSUSB_REG_UGCTRL2_USB0SEL 0x30
50 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
55 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; in board_init()
68 return 0; in board_init()
73 if (fdtdec_setup_mem_size_base() != 0) in dram_init()
76 return 0; in dram_init()
83 return 0; in dram_init_banksize()
[all …]
/openbmc/linux/include/uapi/linux/genwqe/
H A Dgenwqe_card.h36 #define GENWQE_TYPE_ALTERA_230 0x00 /* GenWQE4 Stratix-IV-230 */
37 #define GENWQE_TYPE_ALTERA_530 0x01 /* GenWQE4 Stratix-IV-530 */
38 #define GENWQE_TYPE_ALTERA_A4 0x02 /* GenWQE5 A4 Stratix-V-A4 */
39 #define GENWQE_TYPE_ALTERA_A7 0x03 /* GenWQE5 A7 Stratix-V-A7 */
43 #define GENWQE_SLU_OFFS GENWQE_UID_OFFS(0)
49 #define IO_EXTENDED_ERROR_POINTER 0x00000048
50 #define IO_ERROR_INJECT_SELECTOR 0x00000060
51 #define IO_EXTENDED_DIAG_SELECTOR 0x00000070
52 #define IO_EXTENDED_DIAG_READ_MBX 0x00000078
53 #define IO_EXTENDED_DIAG_MAP(ring) (0x00000500 | ((ring) << 3))
[all …]
/openbmc/u-boot/board/renesas/eagle/
H A Deagle.c29 #define CPGWPR 0xE6150900
30 #define CPGWPCR 0xE6150904
33 #define PLL0CR 0xE61500D8
34 #define PLL0_STC_MASK 0x7F000000
45 writel(0xA5A5A500, &rwdt->rwtcsra); in s_init()
46 writel(0xA5A5A500, &swdt->swtcsra); in s_init()
56 writel(0xA5A5FFFF, CPGWPR); in board_early_init_f()
57 writel(0x5A5A0000, CPGWPCR); in board_early_init_f()
59 return 0; in board_early_init_f()
65 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; in board_init()
[all …]
/openbmc/u-boot/board/renesas/draak/
H A Ddraak.c44 return 0; in board_early_init_f()
48 #define HSUSB_REG_LPSTS 0xE6590102
50 #define HSUSB_REG_UGCTRL2 0xE6590184
51 #define HSUSB_REG_UGCTRL2_USB0SEL 0x30
52 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
57 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; in board_init()
70 return 0; in board_init()
75 if (fdtdec_setup_mem_size_base() != 0) in dram_init()
78 return 0; in dram_init()
85 return 0; in dram_init_banksize()
[all …]

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