/openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | fsl,imx8m-pinctrl.yaml | 81 reg = <0x30330000 0x10000>; 85 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>, 86 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
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/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/ |
H A D | pci_nrtr_regs.h | 22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100 24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120 26 #define mmPCI_NRTR_DBG_E_ARB 0x300 28 #define mmPCI_NRTR_DBG_W_ARB 0x304 30 #define mmPCI_NRTR_DBG_N_ARB 0x308 32 #define mmPCI_NRTR_DBG_S_ARB 0x30C 34 #define mmPCI_NRTR_DBG_L_ARB 0x310 36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320 38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324 40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328 [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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H A D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 [all …]
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H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
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H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 [all …]
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/openbmc/u-boot/include/dt-bindings/pinctrl/ |
H A D | pins-imx8mq.h | 24 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 25 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 26 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 27 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 28 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 29 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 30 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 31 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 32 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 33 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | am4.h | 8 #define AM4_CLKCTRL_OFFSET 0x20 12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120 14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120) 17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228 19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228) 20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230) 23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220 25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220) 26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328) 27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338) [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | imx6sl-pinfunc.h | 17 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 18 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 19 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 20 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 21 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 22 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 23 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 24 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 25 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 26 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
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H A D | imx53-pinfunc.h | 13 #define IMX_PAD_SION 0x40000000 18 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 19 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 20 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 21 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 22 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 23 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 24 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 25 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 26 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 [all …]
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H A D | imx6q-pinfunc.h | 17 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 18 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 19 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 20 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 21 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 22 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 23 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 24 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 25 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 26 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
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H A D | imx53-pinfunc.h | 13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 [all …]
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H A D | imx6q-pinfunc.h | 13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 [all …]
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H A D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 [all …]
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/openbmc/linux/drivers/ntb/hw/amd/ |
H A D | ntb_hw_amd.h | 56 #define NTB_LNK_STA_SPEED_MASK 0x000F0000 57 #define NTB_LNK_STA_WIDTH_MASK 0x03F00000 97 AMD_CNTL_OFFSET = 0x200, 106 AMD_STA_OFFSET = 0x204, 107 AMD_PGSLV_OFFSET = 0x208, 108 AMD_SPAD_MUX_OFFSET = 0x20C, 109 AMD_SPAD_OFFSET = 0x210, 110 AMD_RSMU_HCID = 0x250, 111 AMD_RSMU_SIID = 0x254, 112 AMD_PSION_OFFSET = 0x300, [all …]
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/openbmc/linux/drivers/clk/tegra/ |
H A D | clk-tegra-audio.c | 17 #define AUDIO_SYNC_CLK_I2S0 0x4a0 18 #define AUDIO_SYNC_CLK_I2S1 0x4a4 19 #define AUDIO_SYNC_CLK_I2S2 0x4a8 20 #define AUDIO_SYNC_CLK_I2S3 0x4ac 21 #define AUDIO_SYNC_CLK_I2S4 0x4b0 22 #define AUDIO_SYNC_CLK_SPDIF 0x4b4 23 #define AUDIO_SYNC_CLK_DMIC1 0x560 24 #define AUDIO_SYNC_CLK_DMIC2 0x564 25 #define AUDIO_SYNC_CLK_DMIC3 0x6b8 27 #define AUDIO_SYNC_DOUBLER 0x49c [all …]
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/openbmc/linux/drivers/net/ethernet/broadcom/asp2/ |
H A D | bcmasp_intf_defs.h | 6 ((((intf)->port) * 0x800) + 0xc000) 7 #define UMC_CMD 0x008 8 #define UMC_CMD_TX_EN BIT(0) 10 #define UMC_CMD_SPEED_SHIFT 0x2 11 #define UMC_CMD_SPEED_MASK 0x3 12 #define UMC_CMD_SPEED_10 0x0 13 #define UMC_CMD_SPEED_100 0x1 14 #define UMC_CMD_SPEED_1000 0x2 15 #define UMC_CMD_SPEED_2500 0x3 33 #define UMC_MAC0 0x0c [all …]
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/openbmc/linux/drivers/phy/ralink/ |
H A D | phy-mt7621-pci.c | 18 #define RG_PE1_PIPE_REG 0x02c 22 #define RG_P0_TO_P1_WIDTH 0x100 23 #define RG_PE1_H_LCDDS_REG 0x49c 24 #define RG_PE1_H_LCDDS_PCW GENMASK(30, 0) 26 #define RG_PE1_FRC_H_XTAL_REG 0x400 30 #define RG_PE1_FRC_PHY_REG 0x000 34 #define RG_PE1_H_PLL_REG 0x490 42 #define RG_PE1_H_PLL_FBKSEL_REG 0x4bc 45 #define RG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4 46 #define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0) [all …]
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/openbmc/qemu/hw/net/ |
H A D | mv88w8618_eth.c | 18 #define MP_ETH_SIZE 0x00001000 21 #define MP_ETH_SMIR 0x010 22 #define MP_ETH_PCXR 0x408 23 #define MP_ETH_SDCMR 0x448 24 #define MP_ETH_ICR 0x450 25 #define MP_ETH_IMR 0x458 26 #define MP_ETH_FRDP0 0x480 27 #define MP_ETH_FRDP1 0x484 28 #define MP_ETH_FRDP2 0x488 29 #define MP_ETH_FRDP3 0x48C [all …]
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/openbmc/linux/drivers/media/pci/cx18/ |
H A D | cx18-av-core.h | 32 CX18_AV_SVIDEO_LUMA1 = 0x10, 33 CX18_AV_SVIDEO_LUMA2 = 0x20, 34 CX18_AV_SVIDEO_LUMA3 = 0x30, 35 CX18_AV_SVIDEO_LUMA4 = 0x40, 36 CX18_AV_SVIDEO_LUMA5 = 0x50, 37 CX18_AV_SVIDEO_LUMA6 = 0x60, 38 CX18_AV_SVIDEO_LUMA7 = 0x70, 39 CX18_AV_SVIDEO_LUMA8 = 0x80, 40 CX18_AV_SVIDEO_CHROMA4 = 0x400, 41 CX18_AV_SVIDEO_CHROMA5 = 0x500, [all …]
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/openbmc/linux/drivers/gpu/drm/radeon/ |
H A D | sumod.h | 30 #define RCU_FW_VERSION 0x30c 32 #define RCU_PWR_GATING_SEQ0 0x408 33 #define RCU_PWR_GATING_SEQ1 0x40c 34 #define RCU_PWR_GATING_CNTL 0x410 35 # define PWR_GATING_EN (1 << 0) 36 # define RSVD_MASK (0x3 << 1) 38 # define PCV_MASK (0x1f << 3) 41 # define PCP_MASK (0xf << 8) 44 # define RPW_MASK (0xf << 16) 47 # define ID_MASK (0xf << 24) [all …]
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/openbmc/linux/drivers/net/ethernet/intel/ice/ |
H A D | ice_ptp_hw.h | 128 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL 203 #define ICE_PTP_CLOCK_INDEX_0 0x00 204 #define ICE_PTP_CLOCK_INDEX_1 0x01 211 #define GLTSYN_CMD_INIT_TIME BIT(0) 213 #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1)) 219 #define PHY_CMD_INIT_TIME BIT(0) 221 #define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1)) 222 #define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2)) 223 #define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2)) 225 #define TS_CMD_MASK_E810 0xFF [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-mx5/ |
H A D | iomux-mx53.h | 30 MX53_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL), 31 MX53_PAD_GPIO_19__GPIO4_5 = IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL), 32 MX53_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL), 33 MX53_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL), 34 MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 = IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL), 35 MX53_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL), 36 MX53_PAD_GPIO_19__FEC_TDATA_3 = IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL), 37 MX53_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL), 38 MX53_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL), 39 MX53_PAD_KEY_COL0__GPIO4_6 = IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL), [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
H A D | clk_rst.h | 13 /* pll_out[0] is output A control, pll_out[1] is output B control */ 55 uint crc_rst_src; /* _RST_SOURCE_0,0x00 */ 58 uint crc_reserved0; /* reserved_0, 0x1C */ 59 uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ 60 uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ 61 uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ 62 uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ 63 uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ 64 uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ 65 uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */ [all …]
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