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/openbmc/linux/drivers/bus/
H A Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
/openbmc/linux/drivers/dma/ti/
H A Dk3-psil-priv.h25 * 0x4400 and 0xc400) only the src configuration can be present. If no dst
26 * configuration found the code will look for (dst_thread_id & ~0x8000) to find
H A Dk3-psil-am654.c54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
[all …]
H A Dk3-psil-j721s2.c63 PSIL_PDMA_MCASP(0x4400),
64 PSIL_PDMA_MCASP(0x4401),
65 PSIL_PDMA_MCASP(0x4402),
66 PSIL_PDMA_MCASP(0x4403),
67 PSIL_PDMA_MCASP(0x4404),
69 PSIL_PDMA_XY_PKT(0x4600),
70 PSIL_PDMA_XY_PKT(0x4601),
71 PSIL_PDMA_XY_PKT(0x4602),
72 PSIL_PDMA_XY_PKT(0x4603),
73 PSIL_PDMA_XY_PKT(0x4604),
[all …]
H A Dk3-psil-am62.c73 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
74 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
75 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
76 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
78 PSIL_PDMA_XY_PKT(0x4300),
79 PSIL_PDMA_XY_PKT(0x4301),
80 PSIL_PDMA_XY_PKT(0x4302),
81 PSIL_PDMA_XY_PKT(0x4303),
82 PSIL_PDMA_XY_PKT(0x4304),
83 PSIL_PDMA_XY_PKT(0x4305),
[all …]
H A Dk3-psil-am62a.c83 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
84 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
85 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
86 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
88 PSIL_PDMA_XY_PKT(0x4300),
89 PSIL_PDMA_XY_PKT(0x4301),
90 PSIL_PDMA_XY_PKT(0x4302),
91 PSIL_PDMA_XY_PKT(0x4303),
92 PSIL_PDMA_XY_PKT(0x4304),
93 PSIL_PDMA_XY_PKT(0x4305),
[all …]
H A Dk3-psil-am64.c66 PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
67 PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
68 PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
69 PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
71 PSIL_ETHERNET(0x4100, 21, 48, 16),
72 PSIL_ETHERNET(0x4101, 22, 64, 16),
73 PSIL_ETHERNET(0x4102, 23, 80, 16),
74 PSIL_ETHERNET(0x4103, 24, 96, 16),
76 PSIL_ETHERNET(0x4200, 25, 112, 16),
77 PSIL_ETHERNET(0x4201, 26, 128, 16),
[all …]
H A Dk3-psil-j7200.c64 PSIL_PDMA_MCASP(0x4400),
65 PSIL_PDMA_MCASP(0x4401),
66 PSIL_PDMA_MCASP(0x4402),
68 PSIL_PDMA_XY_PKT(0x4600),
69 PSIL_PDMA_XY_PKT(0x4601),
70 PSIL_PDMA_XY_PKT(0x4602),
71 PSIL_PDMA_XY_PKT(0x4603),
72 PSIL_PDMA_XY_PKT(0x4604),
73 PSIL_PDMA_XY_PKT(0x4605),
74 PSIL_PDMA_XY_PKT(0x4606),
[all …]
H A Dk3-psil-j784s4.c71 PSIL_PDMA_MCASP(0x4400),
72 PSIL_PDMA_MCASP(0x4401),
73 PSIL_PDMA_MCASP(0x4402),
74 PSIL_PDMA_MCASP(0x4403),
75 PSIL_PDMA_MCASP(0x4404),
77 PSIL_PDMA_XY_PKT(0x4600),
78 PSIL_PDMA_XY_PKT(0x4601),
79 PSIL_PDMA_XY_PKT(0x4602),
80 PSIL_PDMA_XY_PKT(0x4603),
81 PSIL_PDMA_XY_PKT(0x4604),
[all …]
H A Dk3-psil-j721e.c72 PSIL_SA2UL(0x4000, 0),
73 PSIL_SA2UL(0x4001, 0),
74 PSIL_SA2UL(0x4002, 0),
75 PSIL_SA2UL(0x4003, 0),
77 PSIL_ETHERNET(0x4100),
78 PSIL_ETHERNET(0x4101),
79 PSIL_ETHERNET(0x4102),
80 PSIL_ETHERNET(0x4103),
82 PSIL_ETHERNET(0x4200),
83 PSIL_ETHERNET(0x4201),
[all …]
/openbmc/u-boot/arch/x86/cpu/braswell/
H A Dearly_uart.c10 (((segbus) & 0xfff) << 20) | \
11 (((dev) & 0x1f) << 15) | \
12 (((fn) & 0x07) << 12))
15 #define LPC_DEV 0x1f
16 #define LPC_FUNC 0
19 #define UART_CONT 0x80
32 #define IO_BASE_ADDRESS 0xfed80000
36 return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 + in gpio_pconf0()
37 family * 0x400 + pad * 8; in gpio_pconf0()
44 clrsetbits_le32(pconf0_addr, 0xf << 16, func << 16); in gpio_select_func()
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dfirewall_s10.h11 u32 nand; /* 0x00 */
15 u32 usb1; /* 0x10 */
19 u32 spim1; /* 0x20 */
23 u32 emac1; /* 0x30 */
27 u32 sdmmc; /* 0x40 */
31 u32 i2c0; /* 0x50 */
35 u32 i2c4; /* 0x60 */
39 u32 uart1; /* 0x70 */
43 u32 _pad_0x00; /* 0x00 */
47 u32 emac0tx_ecc; /* 0x10 */
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv10.c34 u32 pipe_0x0000[0x040/4];
35 u32 pipe_0x0040[0x010/4];
36 u32 pipe_0x0200[0x0c0/4];
37 u32 pipe_0x4400[0x080/4];
38 u32 pipe_0x6400[0x3b0/4];
39 u32 pipe_0x6800[0x2f0/4];
40 u32 pipe_0x6c00[0x030/4];
41 u32 pipe_0x7000[0x130/4];
42 u32 pipe_0x7400[0x0c0/4];
43 u32 pipe_0x7800[0x0c0/4];
[all …]
/openbmc/u-boot/board/renesas/ap325rxa/
H A Dap325rxa.c13 #define PRPRICR5 0xFF800048 /* LMB */
14 #define PRPRICR5_D 0x2a
17 #define FPGA_NAND_CTL 0xB410020C
18 #define FPGA_NAND_RST 0x0008
19 #define FPGA_NAND_INIT 0x0000
23 #define PACR_D 0x0000
24 #define PBCR_D 0x0000
25 #define PCCR_D 0x1000
26 #define PDCR_D 0x0000
27 #define PECR_D 0x0410
[all …]
/openbmc/linux/drivers/regulator/
H A Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/openbmc/u-boot/fs/ext4/
H A Dcrc16.c13 /** CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1) */
15 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
16 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
17 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
18 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
19 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
20 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
21 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
22 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
23 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/linux/lib/
H A Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/u-boot/fs/ubifs/
H A Dcrc16.c11 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
13 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
14 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
15 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
16 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
17 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
18 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
19 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
20 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
21 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Ddavinci-mcasp-audio.yaml35 description: 0 - I2S or 1 - DIT operation mode
37 - 0
52 0 - Inactive, 1 - TX, 2 - RX
58 minimum: 0
83 0 disables the FIFO use
90 0 disables the FIFO use
97 0 - 3-state, 2 - logic low, 3 - logic high
99 - 0
154 const: 0
175 - 0
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-mcu.dtsi11 reg = <0x0 0x40f00000 0x0 0x20000>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
18 reg = <0x4040 0x4>;
26 reg = <0x0 0x40f04200 0x0 0x10>;
29 pinctrl-single,function-mask = <0x00000101>;
35 reg = <0x0 0x40f04280 0x0 0x8>;
38 pinctrl-single,function-mask = <0x00000003>;
43 reg = <0x00 0x40a00000 0x00 0x100>;
53 reg = <0x00 0x41c00000 0x00 0x80000>;
54 ranges = <0x0 0x00 0x41c00000 0x80000>;
[all …]
/openbmc/u-boot/board/intel/cherryhill/
H A Dcherryhill.c11 GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0,
12 VOLT_1_8, NA, NA, NA, 0, ENABLE, 2, SOUTHEAST),
15 GPIO_FAMILY_CONF("GPIO FAMILY TABLE END", NA, 0,
16 VOLT_1_8, NA, NA, NA, 0, DISABLE, 0, TERMINATOR),
22 NA, 29, NA, 0x4c38, NORTH),
25 NA, 27, NA, 0x4c28, NORTH),
28 NA, 20, NA, 0x4858, NORTH),
31 NA, 37, NA, 0x5018, NORTH),
34 NA, 42, NA, 0x5040, NORTH),
37 NA, 35, NA, 0x5008, NORTH),
[all …]
/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_backend.h20 #define SUN4I_BACKEND_MODCTL_REG 0x800
24 #define SUN4I_BACKEND_MODCTL_OUT_LCD0 (0 << 20)
34 #define SUN4I_BACKEND_MODCTL_DEBE_EN BIT(0)
36 #define SUN4I_BACKEND_BACKCOLOR_REG 0x804
39 #define SUN4I_BACKEND_DISSIZE_REG 0x808
40 #define SUN4I_BACKEND_DISSIZE(w, h) (((((h) - 1) & 0xffff) << 16) | \
41 (((w) - 1) & 0xffff))
43 #define SUN4I_BACKEND_LAYSIZE_REG(l) (0x810 + (0x4 * (l)))
44 #define SUN4I_BACKEND_LAYSIZE(w, h) (((((h) - 1) & 0x1fff) << 16) | \
45 (((w) - 1) & 0x1fff))
[all …]
/openbmc/u-boot/board/keymile/common/
H A Divm.c17 0x0000, 0xCC01, 0xD801, 0x1400, in ivm_calc_crc()
18 0xF001, 0x3C00, 0x2800, 0xE401, in ivm_calc_crc()
19 0xA001, 0x6C00, 0x7800, 0xB401, in ivm_calc_crc()
20 0x5000, 0x9C01, 0x8801, 0x4400}; in ivm_calc_crc()
22 unsigned short crc = 0; /* final result */ in ivm_calc_crc()
23 unsigned short r1 = 0; /* temp */ in ivm_calc_crc()
24 unsigned char byte = 0; /* input buffer */ in ivm_calc_crc()
28 for (i = 0; i < len; i++) { in ivm_calc_crc()
32 r1 = crc_tab[crc & 0xF]; in ivm_calc_crc()
33 crc = ((crc) >> 4) & 0x0FFF; in ivm_calc_crc()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da4xx_gpu.c30 for (i = 0; i < submit->nr_cmds; i++) { in a4xx_submit()
61 OUT_RING(ring, 0x00000000); in a4xx_submit()
80 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
81 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
82 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
83 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
84 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
86 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
87 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dsi_vbt.c54 #define MIPI_TRANSFER_MODE_SHIFT 0
59 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
60 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
61 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
62 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
63 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
64 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
65 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
66 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
67 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
[all …]

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