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/openbmc/linux/arch/arm/mach-footbridge/
H A Ddma-isa.c24 #define ISA_DMA_MASK 0
34 { 0x0a, 0x0b, 0x0c, 0x487, 0x087, 0x00, 0x01 },
35 { 0x0a, 0x0b, 0x0c, 0x483, 0x083, 0x02, 0x03 },
36 { 0x0a, 0x0b, 0x0c, 0x481, 0x081, 0x04, 0x05 },
37 { 0x0a, 0x0b, 0x0c, 0x482, 0x082, 0x06, 0x07 },
38 { 0xd4, 0xd6, 0xd8, 0x000, 0x000, 0xc0, 0xc2 },
39 { 0xd4, 0xd6, 0xd8, 0x48b, 0x08b, 0xc4, 0xc6 },
40 { 0xd4, 0xd6, 0xd8, 0x489, 0x089, 0xc8, 0xca },
41 { 0xd4, 0xd6, 0xd8, 0x48a, 0x08a, 0xcc, 0xce }
57 .coherent_dma_mask = ~(dma_addr_t)0,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sdm660-venus.yaml113 reg = <0x0cc00000 0xff000>;
119 interconnects = <&gnoc 0 &mnoc 13>,
123 iommus = <&mmss_smmu 0x400>,
124 <&mmss_smmu 0x401>,
125 <&mmss_smmu 0x40a>,
126 <&mmss_smmu 0x407>,
127 <&mmss_smmu 0x40e>,
128 <&mmss_smmu 0x40f>,
129 <&mmss_smmu 0x408>,
130 <&mmss_smmu 0x409>,
[all …]
/openbmc/linux/arch/arc/include/asm/
H A Dirqflags-arcv2.h21 #define CLRI_STATUS_E_MASK 0xF
24 #define AUX_USER_SP 0x00D
25 #define AUX_IRQ_CTRL 0x00E
26 #define AUX_IRQ_ACT 0x043 /* Active Intr across all levels */
27 #define AUX_IRQ_LVL_PEND 0x200 /* Pending Intr across all levels */
28 #define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
29 #define AUX_IRQ_PRIORITY 0x206
30 #define ICAUSE 0x40a
31 #define AUX_IRQ_SELECT 0x40b
32 #define AUX_IRQ_ENABLE 0x40c
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/openbmc/linux/drivers/staging/media/max96712/
H A Dmax96712.c19 #define MAX96712_ID 0x20
24 MAX96712_PATTERN_CHECKERBOARD = 0,
49 dev_err(&priv->client->dev, "read 0x%04x failed\n", reg); in max96712_read()
62 dev_err(&priv->client->dev, "write 0x%04x failed\n", reg); in max96712_write()
74 dev_err(&priv->client->dev, "update 0x%04x failed\n", reg); in max96712_update_bits()
86 dev_err(&priv->client->dev, "bulk write 0x%04x failed\n", reg); in max96712_write_bulk()
99 values[i - 1] = (val >> ((val_count - i) * 8)) & 0xff; in max96712_write_bulk_value()
106 max96712_update_bits(priv, 0x13, 0x40, 0x40); in max96712_reset()
113 max96712_update_bits(priv, 0x40b, 0x02, 0x02); in max96712_mipi_enable()
114 max96712_update_bits(priv, 0x8a0, 0x80, 0x80); in max96712_mipi_enable()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_d.h27 #define mmIH_VMID_0_LUT 0xf50
28 #define mmIH_VMID_1_LUT 0xf51
29 #define mmIH_VMID_2_LUT 0xf52
30 #define mmIH_VMID_3_LUT 0xf53
31 #define mmIH_VMID_4_LUT 0xf54
32 #define mmIH_VMID_5_LUT 0xf55
33 #define mmIH_VMID_6_LUT 0xf56
34 #define mmIH_VMID_7_LUT 0xf57
35 #define mmIH_VMID_8_LUT 0xf58
36 #define mmIH_VMID_9_LUT 0xf59
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/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a23.c35 .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
36 .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
40 .mr3 = 0,
42 .tpr0 = 0x2ab83def,
43 .tpr1 = 0x18082356,
44 .tpr2 = 0x00034156,
45 .tpr3 = 0x448c5533,
46 .tpr4 = 0x08010d00,
47 .tpr5 = 0x0340b20f,
48 .tpr6 = 0x20d118cc,
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Ddma.h31 #define MAX_DMA_ADDRESS (~0UL)
44 * controller 1: channels 0-3, byte operations, ports 00-1F
49 * - channels 0-3 are byte - addresses/counts are for physical bytes
51 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
54 * - page registers for 5-7 don't use data bit 0, represent 128K pages
55 * - page registers for 0-3 use bit 0, represent 64K pages
61 * Address mapping for channels 0-3:
76 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
84 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
90 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
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/openbmc/linux/include/uapi/linux/
H A Delf.h26 #define PT_NULL 0
34 #define PT_LOOS 0x60000000 /* OS-specific */
35 #define PT_HIOS 0x6fffffff /* OS-specific */
36 #define PT_LOPROC 0x70000000
37 #define PT_HIPROC 0x7fffffff
38 #define PT_GNU_EH_FRAME (PT_LOOS + 0x474e550)
39 #define PT_GNU_STACK (PT_LOOS + 0x474e551)
40 #define PT_GNU_RELRO (PT_LOOS + 0x474e552)
41 #define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
45 #define PT_AARCH64_MEMTAG_MTE (PT_LOPROC + 0x2)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Ddc.h12 /* CMD register 0x000 ~ 0x43 */
14 /* Address 0x000 ~ 0x002 */
21 /* Address 0x008 ~ 0x00a */
28 /* Address 0x010 ~ 0x012 */
35 /* Address 0x018 ~ 0x01a */
42 /* Address 0x028 */
47 /* Address 0x030 ~ 0x033 */
55 /* Address 0x036 ~ 0x03e */
68 /* Address 0x040 ~ 0x043 */
80 /* COM register 0x300 ~ 0x329 */
[all …]
/openbmc/linux/tools/testing/selftests/arm64/fp/
H A Dsve-ptrace.c26 #define NT_ARM_SVE 0x405
30 #define NT_ARM_SSVE 0x40b
78 for (i = 0; i < size; i++) in fill_buf()
164 size_t new_sve_size = 0; in ptrace_set_get_inherit()
168 memset(&sve, 0, sizeof(sve)); in ptrace_set_get_inherit()
173 if (ret != 0) { in ptrace_set_get_inherit()
195 if (ret != 0) { in ptrace_set_get_inherit()
219 size_t new_sve_size = 0; in ptrace_set_get_vl()
234 memset(&sve, 0, sizeof(sve)); in ptrace_set_get_vl()
238 if (ret != 0) { in ptrace_set_get_vl()
[all …]
/openbmc/linux/drivers/gpu/drm/tegra/
H A Ddc.h176 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
177 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
179 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
180 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
181 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
182 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
183 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
184 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
185 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
186 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
[all …]
/openbmc/linux/sound/pci/lx6464es/
H A Dlx_core.c23 0,
24 0x400,
25 0x401,
26 0x402,
27 0x403,
28 0x404,
29 0x405,
30 0x406,
31 0x407,
32 0x408,
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
48 #size-cells = <0>;
53 reg = <0x0 0x100>;
73 reg = <0x0 0x101>;
88 reg = <0x0 0x102>;
103 reg = <0x0 0x103>;
115 CPU4: cpu@0 {
118 reg = <0x0 0x0>;
138 reg = <0x0 0x1>;
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwm2200.h14 #define WM2200_CLKSRC_MCLK1 0
19 #define WM2200_FLL_SRC_MCLK1 0
26 #define WM2200_SOFTWARE_RESET 0x00
27 #define WM2200_DEVICE_REVISION 0x01
28 #define WM2200_TONE_GENERATOR_1 0x0B
29 #define WM2200_CLOCKING_3 0x102
30 #define WM2200_CLOCKING_4 0x103
31 #define WM2200_FLL_CONTROL_1 0x111
32 #define WM2200_FLL_CONTROL_2 0x112
33 #define WM2200_FLL_CONTROL_3 0x113
[all …]
/openbmc/linux/drivers/hwmon/
H A Dnct6775-core.c22 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
23 * nct6116d 9 5 5 3+3 0xd280 0xc1 0x5ca3
24 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
25 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
26 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
27 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
28 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
29 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
30 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
31 * nct6796d 14 7 7 2+6 0xd420 0xc1 0x5ca3
[all …]
/openbmc/linux/fs/smb/client/
H A Dcifspdu.h16 #define CIFS_PROT 0
18 #define BAD_PROT 0xFFFF
21 * Note some commands have minimal (wct=0,bcc=0), or uninteresting, responses
25 #define SMB_COM_CREATE_DIRECTORY 0x00 /* trivial response */
26 #define SMB_COM_DELETE_DIRECTORY 0x01 /* trivial response */
27 #define SMB_COM_CLOSE 0x04 /* triv req/rsp, timestamp ignored */
28 #define SMB_COM_FLUSH 0x05 /* triv req/rsp */
29 #define SMB_COM_DELETE 0x06 /* trivial response */
30 #define SMB_COM_RENAME 0x07 /* trivial response */
31 #define SMB_COM_QUERY_INFORMATION 0x08 /* aka getattr */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
H A Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
H A Ddce_11_2_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Dcore.h22 #define MASKBYTE0 0xff
23 #define MASKBYTE1 0xff00
24 #define MASKBYTE2 0xff0000
25 #define MASKBYTE3 0xff000000
26 #define MASKBYTE4 0xff00000000ULL
27 #define MASKHWORD 0xffff0000
28 #define MASKLWORD 0x0000ffff
29 #define MASKDWORD 0xffffffff
30 #define RFREG_MASK 0xfffff
31 #define INV_RF_DATA 0xffffffff
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dadv7842.c13 * ADV7842 I2C Register Maps, Rev. 0, November 2010
16 * Decoder and Digitizer , Rev. 0, January 2011
38 MODULE_PARM_DESC(debug, "debug level (0-2)");
50 #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0)
51 #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0)
52 #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0)
54 #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5)
61 #define ADV7842_OP_CH_SEL_GBR (0 << 5)
68 #define ADV7842_OP_SWAP_CB_CR (1 << 0)
153 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++) in adv7842_check_dv_timings()
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphy_lcn.c40 #define NOISE_IF_OFF 0
45 #define PAPD2LUT 0
46 #define PAPD_CORR_NORM 0
47 #define PAPD_BLANKING_THRESHOLD 0
48 #define PAPD_STOP_AFTER_LAST_UPDATE 0
70 (0 + 8)
72 (0x7f << LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT)
75 (0 + 8)
77 (0x7f << LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT)
85 (read_phy_reg((pi), 0x451) & \
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/openbmc/linux/drivers/media/dvb-frontends/drx39xyj/
H A Ddrxj_map.h37 * Generated by: IDF:x 1.3.0
56 #define ATV_COMM_EXEC__A 0xC00000
58 #define ATV_COMM_EXEC__M 0x3
59 #define ATV_COMM_EXEC__PRE 0x0
60 #define ATV_COMM_EXEC_STOP 0x0
61 #define ATV_COMM_EXEC_ACTIVE 0x1
62 #define ATV_COMM_EXEC_HOLD 0x2
64 #define ATV_COMM_STATE__A 0xC00001
66 #define ATV_COMM_STATE__M 0xFFFF
67 #define ATV_COMM_STATE__PRE 0x0
[all …]