1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2b8b572e1SStephen Rothwell #ifndef _ASM_POWERPC_DMA_H
3b8b572e1SStephen Rothwell #define _ASM_POWERPC_DMA_H
4b8b572e1SStephen Rothwell #ifdef __KERNEL__
5b8b572e1SStephen Rothwell
6b8b572e1SStephen Rothwell /*
7b8b572e1SStephen Rothwell * Defines for using and allocating dma channels.
8b8b572e1SStephen Rothwell * Written by Hennus Bergman, 1992.
9b8b572e1SStephen Rothwell * High DMA channel support & info by Hannu Savolainen
10b8b572e1SStephen Rothwell * and John Boyd, Nov. 1992.
11b8b572e1SStephen Rothwell * Changes for ppc sound by Christoph Nadig
12b8b572e1SStephen Rothwell */
13b8b572e1SStephen Rothwell
14b8b572e1SStephen Rothwell /*
15b8b572e1SStephen Rothwell * Note: Adapted for PowerPC by Gary Thomas
16b8b572e1SStephen Rothwell * Modified by Cort Dougan <cort@cs.nmt.edu>
17b8b572e1SStephen Rothwell *
18b8b572e1SStephen Rothwell * None of this really applies for Power Macintoshes. There is
19b8b572e1SStephen Rothwell * basically just enough here to get kernel/dma.c to compile.
20b8b572e1SStephen Rothwell */
21b8b572e1SStephen Rothwell
22b8b572e1SStephen Rothwell #include <asm/io.h>
23b8b572e1SStephen Rothwell #include <linux/spinlock.h>
24b8b572e1SStephen Rothwell
25b8b572e1SStephen Rothwell #ifndef MAX_DMA_CHANNELS
26b8b572e1SStephen Rothwell #define MAX_DMA_CHANNELS 8
27b8b572e1SStephen Rothwell #endif
28b8b572e1SStephen Rothwell
29b8b572e1SStephen Rothwell /* The maximum address that we can perform a DMA transfer to on this platform */
30b8b572e1SStephen Rothwell /* Doesn't really apply... */
31b8b572e1SStephen Rothwell #define MAX_DMA_ADDRESS (~0UL)
32b8b572e1SStephen Rothwell
33b8b572e1SStephen Rothwell #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
34b8b572e1SStephen Rothwell #define dma_outb outb_p
35b8b572e1SStephen Rothwell #else
36b8b572e1SStephen Rothwell #define dma_outb outb
37b8b572e1SStephen Rothwell #endif
38b8b572e1SStephen Rothwell
39b8b572e1SStephen Rothwell #define dma_inb inb
40b8b572e1SStephen Rothwell
41b8b572e1SStephen Rothwell /*
42b8b572e1SStephen Rothwell * NOTES about DMA transfers:
43b8b572e1SStephen Rothwell *
44b8b572e1SStephen Rothwell * controller 1: channels 0-3, byte operations, ports 00-1F
45b8b572e1SStephen Rothwell * controller 2: channels 4-7, word operations, ports C0-DF
46b8b572e1SStephen Rothwell *
47b8b572e1SStephen Rothwell * - ALL registers are 8 bits only, regardless of transfer size
48b8b572e1SStephen Rothwell * - channel 4 is not used - cascades 1 into 2.
49b8b572e1SStephen Rothwell * - channels 0-3 are byte - addresses/counts are for physical bytes
50b8b572e1SStephen Rothwell * - channels 5-7 are word - addresses/counts are for physical words
51b8b572e1SStephen Rothwell * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
52b8b572e1SStephen Rothwell * - transfer count loaded to registers is 1 less than actual count
53b8b572e1SStephen Rothwell * - controller 2 offsets are all even (2x offsets for controller 1)
54b8b572e1SStephen Rothwell * - page registers for 5-7 don't use data bit 0, represent 128K pages
55b8b572e1SStephen Rothwell * - page registers for 0-3 use bit 0, represent 64K pages
56b8b572e1SStephen Rothwell *
57b8b572e1SStephen Rothwell * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
58b8b572e1SStephen Rothwell * Note that addresses loaded into registers must be _physical_ addresses,
59b8b572e1SStephen Rothwell * not logical addresses (which may differ if paging is active).
60b8b572e1SStephen Rothwell *
61b8b572e1SStephen Rothwell * Address mapping for channels 0-3:
62b8b572e1SStephen Rothwell *
63b8b572e1SStephen Rothwell * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
64b8b572e1SStephen Rothwell * | ... | | ... | | ... |
65b8b572e1SStephen Rothwell * | ... | | ... | | ... |
66b8b572e1SStephen Rothwell * | ... | | ... | | ... |
67b8b572e1SStephen Rothwell * P7 ... P0 A7 ... A0 A7 ... A0
68b8b572e1SStephen Rothwell * | Page | Addr MSB | Addr LSB | (DMA registers)
69b8b572e1SStephen Rothwell *
70b8b572e1SStephen Rothwell * Address mapping for channels 5-7:
71b8b572e1SStephen Rothwell *
72b8b572e1SStephen Rothwell * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
73b8b572e1SStephen Rothwell * | ... | \ \ ... \ \ \ ... \ \
74b8b572e1SStephen Rothwell * | ... | \ \ ... \ \ \ ... \ (not used)
75b8b572e1SStephen Rothwell * | ... | \ \ ... \ \ \ ... \
76b8b572e1SStephen Rothwell * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
77b8b572e1SStephen Rothwell * | Page | Addr MSB | Addr LSB | (DMA registers)
78b8b572e1SStephen Rothwell *
79b8b572e1SStephen Rothwell * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
80b8b572e1SStephen Rothwell * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
81b8b572e1SStephen Rothwell * the hardware level, so odd-byte transfers aren't possible).
82b8b572e1SStephen Rothwell *
83b8b572e1SStephen Rothwell * Transfer count (_not # bytes_) is limited to 64K, represented as actual
84b8b572e1SStephen Rothwell * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
85b8b572e1SStephen Rothwell * and up to 128K bytes may be transferred on channels 5-7 in one operation.
86b8b572e1SStephen Rothwell *
87b8b572e1SStephen Rothwell */
88b8b572e1SStephen Rothwell
89b8b572e1SStephen Rothwell /* 8237 DMA controllers */
90b8b572e1SStephen Rothwell #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
91b8b572e1SStephen Rothwell #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
92b8b572e1SStephen Rothwell
93b8b572e1SStephen Rothwell /* DMA controller registers */
94b8b572e1SStephen Rothwell #define DMA1_CMD_REG 0x08 /* command register (w) */
95b8b572e1SStephen Rothwell #define DMA1_STAT_REG 0x08 /* status register (r) */
96b8b572e1SStephen Rothwell #define DMA1_REQ_REG 0x09 /* request register (w) */
97b8b572e1SStephen Rothwell #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
98b8b572e1SStephen Rothwell #define DMA1_MODE_REG 0x0B /* mode register (w) */
99b8b572e1SStephen Rothwell #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
100b8b572e1SStephen Rothwell #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
101b8b572e1SStephen Rothwell #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
102b8b572e1SStephen Rothwell #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
103b8b572e1SStephen Rothwell #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
104b8b572e1SStephen Rothwell
105b8b572e1SStephen Rothwell #define DMA2_CMD_REG 0xD0 /* command register (w) */
106b8b572e1SStephen Rothwell #define DMA2_STAT_REG 0xD0 /* status register (r) */
107b8b572e1SStephen Rothwell #define DMA2_REQ_REG 0xD2 /* request register (w) */
108b8b572e1SStephen Rothwell #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
109b8b572e1SStephen Rothwell #define DMA2_MODE_REG 0xD6 /* mode register (w) */
110b8b572e1SStephen Rothwell #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
111b8b572e1SStephen Rothwell #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
112b8b572e1SStephen Rothwell #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
113b8b572e1SStephen Rothwell #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
114b8b572e1SStephen Rothwell #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
115b8b572e1SStephen Rothwell
116b8b572e1SStephen Rothwell #define DMA_ADDR_0 0x00 /* DMA address registers */
117b8b572e1SStephen Rothwell #define DMA_ADDR_1 0x02
118b8b572e1SStephen Rothwell #define DMA_ADDR_2 0x04
119b8b572e1SStephen Rothwell #define DMA_ADDR_3 0x06
120b8b572e1SStephen Rothwell #define DMA_ADDR_4 0xC0
121b8b572e1SStephen Rothwell #define DMA_ADDR_5 0xC4
122b8b572e1SStephen Rothwell #define DMA_ADDR_6 0xC8
123b8b572e1SStephen Rothwell #define DMA_ADDR_7 0xCC
124b8b572e1SStephen Rothwell
125b8b572e1SStephen Rothwell #define DMA_CNT_0 0x01 /* DMA count registers */
126b8b572e1SStephen Rothwell #define DMA_CNT_1 0x03
127b8b572e1SStephen Rothwell #define DMA_CNT_2 0x05
128b8b572e1SStephen Rothwell #define DMA_CNT_3 0x07
129b8b572e1SStephen Rothwell #define DMA_CNT_4 0xC2
130b8b572e1SStephen Rothwell #define DMA_CNT_5 0xC6
131b8b572e1SStephen Rothwell #define DMA_CNT_6 0xCA
132b8b572e1SStephen Rothwell #define DMA_CNT_7 0xCE
133b8b572e1SStephen Rothwell
134b8b572e1SStephen Rothwell #define DMA_LO_PAGE_0 0x87 /* DMA page registers */
135b8b572e1SStephen Rothwell #define DMA_LO_PAGE_1 0x83
136b8b572e1SStephen Rothwell #define DMA_LO_PAGE_2 0x81
137b8b572e1SStephen Rothwell #define DMA_LO_PAGE_3 0x82
138b8b572e1SStephen Rothwell #define DMA_LO_PAGE_5 0x8B
139b8b572e1SStephen Rothwell #define DMA_LO_PAGE_6 0x89
140b8b572e1SStephen Rothwell #define DMA_LO_PAGE_7 0x8A
141b8b572e1SStephen Rothwell
142b8b572e1SStephen Rothwell #define DMA_HI_PAGE_0 0x487 /* DMA page registers */
143b8b572e1SStephen Rothwell #define DMA_HI_PAGE_1 0x483
144b8b572e1SStephen Rothwell #define DMA_HI_PAGE_2 0x481
145b8b572e1SStephen Rothwell #define DMA_HI_PAGE_3 0x482
146b8b572e1SStephen Rothwell #define DMA_HI_PAGE_5 0x48B
147b8b572e1SStephen Rothwell #define DMA_HI_PAGE_6 0x489
148b8b572e1SStephen Rothwell #define DMA_HI_PAGE_7 0x48A
149b8b572e1SStephen Rothwell
150b8b572e1SStephen Rothwell #define DMA1_EXT_REG 0x40B
151b8b572e1SStephen Rothwell #define DMA2_EXT_REG 0x4D6
152b8b572e1SStephen Rothwell
153b8b572e1SStephen Rothwell #ifndef __powerpc64__
154b77afad8SMike Rapoport /* in arch/powerpc/kernel/setup_32.c -- Cort */
155b8b572e1SStephen Rothwell extern unsigned int DMA_MODE_WRITE;
156b8b572e1SStephen Rothwell extern unsigned int DMA_MODE_READ;
157b8b572e1SStephen Rothwell #else
158b8b572e1SStephen Rothwell #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
159b8b572e1SStephen Rothwell #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
160b8b572e1SStephen Rothwell #endif
161b8b572e1SStephen Rothwell
162b8b572e1SStephen Rothwell #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
163b8b572e1SStephen Rothwell
164b8b572e1SStephen Rothwell #define DMA_AUTOINIT 0x10
165b8b572e1SStephen Rothwell
166b8b572e1SStephen Rothwell extern spinlock_t dma_spin_lock;
167b8b572e1SStephen Rothwell
claim_dma_lock(void)168b8b572e1SStephen Rothwell static __inline__ unsigned long claim_dma_lock(void)
169b8b572e1SStephen Rothwell {
170b8b572e1SStephen Rothwell unsigned long flags;
171b8b572e1SStephen Rothwell spin_lock_irqsave(&dma_spin_lock, flags);
172b8b572e1SStephen Rothwell return flags;
173b8b572e1SStephen Rothwell }
174b8b572e1SStephen Rothwell
release_dma_lock(unsigned long flags)175b8b572e1SStephen Rothwell static __inline__ void release_dma_lock(unsigned long flags)
176b8b572e1SStephen Rothwell {
177b8b572e1SStephen Rothwell spin_unlock_irqrestore(&dma_spin_lock, flags);
178b8b572e1SStephen Rothwell }
179b8b572e1SStephen Rothwell
180b8b572e1SStephen Rothwell /* enable/disable a specific DMA channel */
enable_dma(unsigned int dmanr)181b8b572e1SStephen Rothwell static __inline__ void enable_dma(unsigned int dmanr)
182b8b572e1SStephen Rothwell {
183b8b572e1SStephen Rothwell unsigned char ucDmaCmd = 0x00;
184b8b572e1SStephen Rothwell
185b8b572e1SStephen Rothwell if (dmanr != 4) {
186b8b572e1SStephen Rothwell dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */
187b8b572e1SStephen Rothwell dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */
188b8b572e1SStephen Rothwell }
189b8b572e1SStephen Rothwell if (dmanr <= 3) {
190b8b572e1SStephen Rothwell dma_outb(dmanr, DMA1_MASK_REG);
191b8b572e1SStephen Rothwell dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */
192b8b572e1SStephen Rothwell } else {
193b8b572e1SStephen Rothwell dma_outb(dmanr & 3, DMA2_MASK_REG);
194b8b572e1SStephen Rothwell }
195b8b572e1SStephen Rothwell }
196b8b572e1SStephen Rothwell
disable_dma(unsigned int dmanr)197b8b572e1SStephen Rothwell static __inline__ void disable_dma(unsigned int dmanr)
198b8b572e1SStephen Rothwell {
199b8b572e1SStephen Rothwell if (dmanr <= 3)
200b8b572e1SStephen Rothwell dma_outb(dmanr | 4, DMA1_MASK_REG);
201b8b572e1SStephen Rothwell else
202b8b572e1SStephen Rothwell dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
203b8b572e1SStephen Rothwell }
204b8b572e1SStephen Rothwell
205b8b572e1SStephen Rothwell /* Clear the 'DMA Pointer Flip Flop'.
206b8b572e1SStephen Rothwell * Write 0 for LSB/MSB, 1 for MSB/LSB access.
207b8b572e1SStephen Rothwell * Use this once to initialize the FF to a known state.
208b8b572e1SStephen Rothwell * After that, keep track of it. :-)
209b8b572e1SStephen Rothwell * --- In order to do that, the DMA routines below should ---
210b8b572e1SStephen Rothwell * --- only be used while interrupts are disabled! ---
211b8b572e1SStephen Rothwell */
clear_dma_ff(unsigned int dmanr)212b8b572e1SStephen Rothwell static __inline__ void clear_dma_ff(unsigned int dmanr)
213b8b572e1SStephen Rothwell {
214b8b572e1SStephen Rothwell if (dmanr <= 3)
215b8b572e1SStephen Rothwell dma_outb(0, DMA1_CLEAR_FF_REG);
216b8b572e1SStephen Rothwell else
217b8b572e1SStephen Rothwell dma_outb(0, DMA2_CLEAR_FF_REG);
218b8b572e1SStephen Rothwell }
219b8b572e1SStephen Rothwell
220b8b572e1SStephen Rothwell /* set mode (above) for a specific DMA channel */
set_dma_mode(unsigned int dmanr,char mode)221b8b572e1SStephen Rothwell static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
222b8b572e1SStephen Rothwell {
223b8b572e1SStephen Rothwell if (dmanr <= 3)
224b8b572e1SStephen Rothwell dma_outb(mode | dmanr, DMA1_MODE_REG);
225b8b572e1SStephen Rothwell else
226b8b572e1SStephen Rothwell dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
227b8b572e1SStephen Rothwell }
228b8b572e1SStephen Rothwell
229b8b572e1SStephen Rothwell /* Set only the page register bits of the transfer address.
230b8b572e1SStephen Rothwell * This is used for successive transfers when we know the contents of
231b8b572e1SStephen Rothwell * the lower 16 bits of the DMA current address register, but a 64k boundary
232b8b572e1SStephen Rothwell * may have been crossed.
233b8b572e1SStephen Rothwell */
set_dma_page(unsigned int dmanr,int pagenr)234b8b572e1SStephen Rothwell static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
235b8b572e1SStephen Rothwell {
236b8b572e1SStephen Rothwell switch (dmanr) {
237b8b572e1SStephen Rothwell case 0:
238b8b572e1SStephen Rothwell dma_outb(pagenr, DMA_LO_PAGE_0);
239b8b572e1SStephen Rothwell dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
240b8b572e1SStephen Rothwell break;
241b8b572e1SStephen Rothwell case 1:
242b8b572e1SStephen Rothwell dma_outb(pagenr, DMA_LO_PAGE_1);
243b8b572e1SStephen Rothwell dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
244b8b572e1SStephen Rothwell break;
245b8b572e1SStephen Rothwell case 2:
246b8b572e1SStephen Rothwell dma_outb(pagenr, DMA_LO_PAGE_2);
247b8b572e1SStephen Rothwell dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
248b8b572e1SStephen Rothwell break;
249b8b572e1SStephen Rothwell case 3:
250b8b572e1SStephen Rothwell dma_outb(pagenr, DMA_LO_PAGE_3);
251b8b572e1SStephen Rothwell dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
252b8b572e1SStephen Rothwell break;
253b8b572e1SStephen Rothwell case 5:
254b8b572e1SStephen Rothwell dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
255b8b572e1SStephen Rothwell dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
256b8b572e1SStephen Rothwell break;
257b8b572e1SStephen Rothwell case 6:
258b8b572e1SStephen Rothwell dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
259b8b572e1SStephen Rothwell dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
260b8b572e1SStephen Rothwell break;
261b8b572e1SStephen Rothwell case 7:
262b8b572e1SStephen Rothwell dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
263b8b572e1SStephen Rothwell dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
264b8b572e1SStephen Rothwell break;
265b8b572e1SStephen Rothwell }
266b8b572e1SStephen Rothwell }
267b8b572e1SStephen Rothwell
268b8b572e1SStephen Rothwell /* Set transfer address & page bits for specific DMA channel.
269b8b572e1SStephen Rothwell * Assumes dma flipflop is clear.
270b8b572e1SStephen Rothwell */
set_dma_addr(unsigned int dmanr,unsigned int phys)271b8b572e1SStephen Rothwell static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
272b8b572e1SStephen Rothwell {
273b8b572e1SStephen Rothwell if (dmanr <= 3) {
274b8b572e1SStephen Rothwell dma_outb(phys & 0xff,
275b8b572e1SStephen Rothwell ((dmanr & 3) << 1) + IO_DMA1_BASE);
276b8b572e1SStephen Rothwell dma_outb((phys >> 8) & 0xff,
277b8b572e1SStephen Rothwell ((dmanr & 3) << 1) + IO_DMA1_BASE);
278b8b572e1SStephen Rothwell } else {
279b8b572e1SStephen Rothwell dma_outb((phys >> 1) & 0xff,
280b8b572e1SStephen Rothwell ((dmanr & 3) << 2) + IO_DMA2_BASE);
281b8b572e1SStephen Rothwell dma_outb((phys >> 9) & 0xff,
282b8b572e1SStephen Rothwell ((dmanr & 3) << 2) + IO_DMA2_BASE);
283b8b572e1SStephen Rothwell }
284b8b572e1SStephen Rothwell set_dma_page(dmanr, phys >> 16);
285b8b572e1SStephen Rothwell }
286b8b572e1SStephen Rothwell
287b8b572e1SStephen Rothwell
288b8b572e1SStephen Rothwell /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
289b8b572e1SStephen Rothwell * a specific DMA channel.
290b8b572e1SStephen Rothwell * You must ensure the parameters are valid.
291b8b572e1SStephen Rothwell * NOTE: from a manual: "the number of transfers is one more
292b8b572e1SStephen Rothwell * than the initial word count"! This is taken into account.
293b8b572e1SStephen Rothwell * Assumes dma flip-flop is clear.
294b8b572e1SStephen Rothwell * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
295b8b572e1SStephen Rothwell */
set_dma_count(unsigned int dmanr,unsigned int count)296b8b572e1SStephen Rothwell static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
297b8b572e1SStephen Rothwell {
298b8b572e1SStephen Rothwell count--;
299b8b572e1SStephen Rothwell if (dmanr <= 3) {
300b8b572e1SStephen Rothwell dma_outb(count & 0xff,
301b8b572e1SStephen Rothwell ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
302b8b572e1SStephen Rothwell dma_outb((count >> 8) & 0xff,
303b8b572e1SStephen Rothwell ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
304b8b572e1SStephen Rothwell } else {
305b8b572e1SStephen Rothwell dma_outb((count >> 1) & 0xff,
306b8b572e1SStephen Rothwell ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
307b8b572e1SStephen Rothwell dma_outb((count >> 9) & 0xff,
308b8b572e1SStephen Rothwell ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
309b8b572e1SStephen Rothwell }
310b8b572e1SStephen Rothwell }
311b8b572e1SStephen Rothwell
312b8b572e1SStephen Rothwell
313b8b572e1SStephen Rothwell /* Get DMA residue count. After a DMA transfer, this
314b8b572e1SStephen Rothwell * should return zero. Reading this while a DMA transfer is
315b8b572e1SStephen Rothwell * still in progress will return unpredictable results.
316b8b572e1SStephen Rothwell * If called before the channel has been used, it may return 1.
317b8b572e1SStephen Rothwell * Otherwise, it returns the number of _bytes_ left to transfer.
318b8b572e1SStephen Rothwell *
319b8b572e1SStephen Rothwell * Assumes DMA flip-flop is clear.
320b8b572e1SStephen Rothwell */
get_dma_residue(unsigned int dmanr)321b8b572e1SStephen Rothwell static __inline__ int get_dma_residue(unsigned int dmanr)
322b8b572e1SStephen Rothwell {
323b8b572e1SStephen Rothwell unsigned int io_port = (dmanr <= 3)
324b8b572e1SStephen Rothwell ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
325b8b572e1SStephen Rothwell : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
326b8b572e1SStephen Rothwell
327b8b572e1SStephen Rothwell /* using short to get 16-bit wrap around */
328b8b572e1SStephen Rothwell unsigned short count;
329b8b572e1SStephen Rothwell
330b8b572e1SStephen Rothwell count = 1 + dma_inb(io_port);
331b8b572e1SStephen Rothwell count += dma_inb(io_port) << 8;
332b8b572e1SStephen Rothwell
333b8b572e1SStephen Rothwell return (dmanr <= 3) ? count : (count << 1);
334b8b572e1SStephen Rothwell }
335b8b572e1SStephen Rothwell
336b8b572e1SStephen Rothwell /* These are in kernel/dma.c: */
337b8b572e1SStephen Rothwell
338b8b572e1SStephen Rothwell /* reserve a DMA channel */
339b8b572e1SStephen Rothwell extern int request_dma(unsigned int dmanr, const char *device_id);
340b8b572e1SStephen Rothwell /* release it again */
341b8b572e1SStephen Rothwell extern void free_dma(unsigned int dmanr);
342b8b572e1SStephen Rothwell
343b8b572e1SStephen Rothwell #endif /* __KERNEL__ */
344b8b572e1SStephen Rothwell #endif /* _ASM_POWERPC_DMA_H */
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