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Searched +full:0 +full:x40048000 (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Dlpc32xx-tsc.txt13 reg = <0x40048000 0x1000>;
15 interrupts = <39 0>;
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dnxp,lpc3220-adc.yaml44 reg = <0x40048000 0x1000>;
46 interrupts = <39 0>;
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dnxp,lpc3220-mic.txt25 reg = <0x40008000 0x4000>;
32 reg = <0x4000c000 0x4000>;
37 interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
43 reg = <0x40010000 0x4000>;
55 reg = <0x40048000 0x1000>;
/openbmc/u-boot/arch/arm/dts/
H A Dvf.dtsi37 reg = <0x40000000 0x00070000>;
42 reg = <0x40027000 0x1000>;
48 reg = <0x40028000 0x1000>;
54 reg = <0x40029000 0x1000>;
60 reg = <0x4002a000 0x1000>;
66 #size-cells = <0>;
68 reg = <0x4002c000 0x1000>;
75 #size-cells = <0>;
77 reg = <0x4002d000 0x1000>;
84 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
/openbmc/linux/arch/arm/mach-lpc32xx/
H A Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvfxxx.dtsi33 #clock-cells = <0>;
39 #clock-cells = <0>;
46 offset = <0x0>;
47 mask = <0x1000>;
66 reg = <0x40000000 0x00070000>;
71 reg = <0x40001000 0x800>;
76 reg = <0x40001800 0x400>;
85 reg = <0x40018000 0x2000>,
86 <0x40024000 0x1000>,
87 <0x40025000 0x1000>;
[all …]
/openbmc/qemu/hw/arm/
H A Dstellaris.c37 #define GPIO_A 0
45 #define BP_OLED_I2C 0x01
46 #define BP_OLED_SSI 0x02
47 #define BP_GAMEPAD 0x04
101 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
105 0x31c0, /* 1 Mhz */
106 0x1ae0, /* 1.8432 Mhz */
107 0x18c0, /* 2 Mhz */
108 0xd573, /* 2.4576 Mhz */
109 0x37a6, /* 3.57954 Mhz */
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Dcache.json4 "EventCode": "0x51",
8 "UMask": "0x1"
12 "EventCode": "0x48",
16 "UMask": "0x2"
20 "EventCode": "0x48",
24 "UMask": "0x1"
29 "EventCode": "0x48",
33 "UMask": "0x1"
39 "EventCode": "0x48",
42 "UMask": "0x1"
[all …]