Home
last modified time | relevance | path

Searched +full:0 +full:x40030000 (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/arch/m68k/fpsp040/
H A Dstan.S27 | k = N mod 2, so in particular, k = 0 or 1.
62 BOUNDS1: .long 0x3FD78000,0x4004BC7E
63 TWOBYPI: .long 0x3FE45F30,0x6DC9C883
65 TANQ4: .long 0x3EA0B759,0xF50F8688
66 TANP3: .long 0xBEF2BAA5,0xA8924F04
68 TANQ3: .long 0xBF346F59,0xB39BA65F,0x00000000,0x00000000
70 TANP2: .long 0x3FF60000,0xE073D3FC,0x199C4A00,0x00000000
72 TANQ2: .long 0x3FF90000,0xD23CD684,0x15D95FA1,0x00000000
74 TANP1: .long 0xBFFC0000,0x8895A6C5,0xFB423BCA,0x00000000
76 TANQ1: .long 0xBFFD0000,0xEEF57E0D,0xA84BC8CE,0x00000000
[all …]
/openbmc/linux/drivers/gpu/drm/msm/
H A Dmsm_mdss.h11 /* can be read from register 0x58 */
20 #define UBWC_1_0 0x10000000
21 #define UBWC_2_0 0x20000000
22 #define UBWC_3_0 0x30000000
23 #define UBWC_4_0 0x40000000
24 #define UBWC_4_3 0x40030000
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dsprd,spi-adi.yaml72 triggered by hardware automatically, channel id 0-1 are for software
95 reg = <0 0x40030000 0 0x10000>;
96 hwlocks = <&hwlock1 0>;
99 #size-cells = <0>;
100 sprd,hw-channels = <30 0x8c20>;
/openbmc/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxilinx_dma.txt56 0-255. Setting this value to zero disables the delay timer interrupt.
93 reg = < 0x40030000 0x10000 >;
94 dma-ranges = <0x00000000 0x00000000 0x40000000>;
95 xlnx,num-fstores = <0x8>;
96 xlnx,flush-fsync = <0x1>;
97 xlnx,addrwidth = <0x20>;
98 clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
103 interrupts = < 0 54 4 >;
104 xlnx,datawidth = <0x40>;
108 interrupts = < 0 53 4 >;
[all …]
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi24 reg = <0 0x20210000 0 0x10000>;
29 reg = <0 0x402b0000 0 0x10000>;
34 reg = <0 0x402e0000 0 0x10000>;
39 reg = <0 0x40400000 0 0x10000>;
44 reg = <0 0x415e0000 0 0x1000000>;
49 reg = <0 0x61100000 0 0x10000>;
54 reg = <0 0x62100000 0 0x10000>;
59 reg = <0 0x63100000 0 0x10000>;
64 reg = <0 0x70b00000 0 0x40000>;
71 ranges = <0 0x0 0x70000000 0x10000000>;
[all …]
/openbmc/u-boot/test/lib/
H A Dlmb.c20 ut_asserteq(lmb->memory.region[0].base, ram_base); in check_lmb()
21 ut_asserteq(lmb->memory.region[0].size, ram_size); in check_lmb()
25 if (num_reserved > 0) { in check_lmb()
26 ut_asserteq(lmb->reserved.region[0].base, base1); in check_lmb()
27 ut_asserteq(lmb->reserved.region[0].size, size1); in check_lmb()
37 return 0; in check_lmb()
56 const phys_addr_t alloc_64k_end = alloc_64k_addr + 0x10000; in test_multi_alloc()
63 ut_assert(ram_end == 0 || ram_end > ram); in test_multi_alloc()
73 ut_asserteq(ret, 0); in test_multi_alloc()
77 ut_asserteq(ret, 0); in test_multi_alloc()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
34 cpu-release-addr = <0 0x4000c204>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/m68k/ifpsp060/
H A Dfpsp.sa1 .long 0x60ff0000,0x17400000,0x60ff0000,0x15f40000
2 .long 0x60ff0000,0x02b60000,0x60ff0000,0x04700000
3 .long 0x60ff0000,0x1b100000,0x60ff0000,0x19aa0000
4 .long 0x60ff0000,0x1b5a0000,0x60ff0000,0x062e0000
5 .long 0x60ff0000,0x102c0000,0x51fc51fc,0x51fc51fc
6 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
7 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
8 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
9 .long 0x2f00203a,0xff2c487b,0x0930ffff,0xfef8202f
10 .long 0x00044e74,0x00042f00,0x203afef2,0x487b0930
[all …]
/openbmc/linux/arch/arm/mach-lpc32xx/
H A Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
/openbmc/qemu/hw/arm/
H A Dmps2.c130 memory_region_init_alias(mr, NULL, name, orig, 0, in make_ram_alias()
166 * 0x21000000 .. 0x21ffffff : PSRAM (16MB) in mps2_common_init()
168 * 0x00000000 .. 0x003fffff : ZBT SSRAM1 in mps2_common_init()
169 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 in mps2_common_init()
170 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 in mps2_common_init()
171 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 in mps2_common_init()
173 * 0x01000000 .. 0x01003fff : block RAM (16K) in mps2_common_init()
174 * 0x01004000 .. 0x01007fff : mirror of above in mps2_common_init()
175 * 0x01008000 .. 0x0100bfff : mirror of above in mps2_common_init()
176 * 0x0100c000 .. 0x0100ffff : mirror of above in mps2_common_init()
[all …]
H A Dstellaris.c37 #define GPIO_A 0
45 #define BP_OLED_I2C 0x01
46 #define BP_OLED_SSI 0x02
47 #define BP_GAMEPAD 0x04
101 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
105 0x31c0, /* 1 Mhz */
106 0x1ae0, /* 1.8432 Mhz */
107 0x18c0, /* 2 Mhz */
108 0xd573, /* 2.4576 Mhz */
109 0x37a6, /* 3.57954 Mhz */
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvfxxx.dtsi33 #clock-cells = <0>;
39 #clock-cells = <0>;
46 offset = <0x0>;
47 mask = <0x1000>;
66 reg = <0x40000000 0x00070000>;
71 reg = <0x40001000 0x800>;
76 reg = <0x40001800 0x400>;
85 reg = <0x40018000 0x2000>,
86 <0x40024000 0x1000>,
87 <0x40025000 0x1000>;
[all …]
/openbmc/linux/arch/m68k/ifpsp060/src/
H A Dfplsp.S37 short 0x0000
39 short 0x0000
41 short 0x0000
44 short 0x0000
46 short 0x0000
48 short 0x0000
51 short 0x0000
53 short 0x0000
55 short 0x0000
58 short 0x0000
[all …]
H A Dfpsp.S43 set _off_bsun, 0x00
44 set _off_snan, 0x04
45 set _off_operr, 0x08
46 set _off_ovfl, 0x0c
47 set _off_unfl, 0x10
48 set _off_dz, 0x14
49 set _off_inex, 0x18
50 set _off_fline, 0x1c
51 set _off_fpu_dis, 0x20
52 set _off_trap, 0x24
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]