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/openbmc/linux/arch/arm/mach-omap2/
H A Dfb.c32 DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"),
33 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
34 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
35 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
36 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
40 DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"),
41 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
42 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
43 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
44 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dcpu.h11 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
12 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
13 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
14 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
16 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
17 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
18 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
20 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
21 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
22 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dti,am654-hbmc.yaml31 "^flash@[0-1],[0-9a-f]+$":
54 reg = <0x0 0x47034000 0x0 0x100>,
55 <0x5 0x00000000 0x1 0x0000000>;
56 ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
57 <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */
58 clocks = <&k3_clks 102 0>;
62 mux-controls = <&hbmc_mux 0>;
64 flash@0,0 {
66 reg = <0x0 0x0 0x4000000>;
H A Dmxicy,nand-ecc-engine.yaml36 reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
38 clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
41 #size-cells = <0>;
43 flash@0 {
45 reg = <0>;
52 reg = <0x43c40000 0x10000>;
59 reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
61 clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
64 #size-cells = <0>;
67 flash@0 {
[all …]
H A Dqcom,nandc.yaml153 reg = <0x1ac00000 0x800>;
165 #size-cells = <0>;
167 nand@0 {
168 reg = <0>;
173 qcom,boot-partitions = <0x0 0x58a0000>;
180 partition@0 {
182 reg = <0 0x58a0000>;
187 reg = <0x58a0000 0x4000000>;
196 reg = <0x79b0000 0x1000>;
202 dmas = <&qpicbam 0>,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/openbmc/linux/arch/arm/boot/compressed/
H A Dmisc.c16 * which should point to addresses in RAM and cleared to 0 on start.
40 int status, i = 0x4000000; in icedcc_putc()
43 if (--i < 0) in icedcc_putc()
46 asm volatile ("mrc p14, 0, %0, c0, c1, 0" : "=r" (status)); in icedcc_putc()
49 asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); in icedcc_putc()
57 int status, i = 0x4000000; in icedcc_putc()
60 if (--i < 0) in icedcc_putc()
63 asm volatile ("mrc p14, 0, %0, c14, c0, 0" : "=r" (status)); in icedcc_putc()
66 asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch)); in icedcc_putc()
73 int status, i = 0x4000000; in icedcc_putc()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dti_qspi.txt23 parameters for Mode-0 and Mode-3 operations, which needs to be set up by
24 the bootloader (U-Boot). Default configuration only supports Mode-0
34 reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
37 #size-cells = <0>;
45 reg = <0x4b300000 0x100>,
46 <0x5c000000 0x4000000>,
48 syscon-chipselects = <&scm_conf 0x558>;
50 #size-cells = <0>;
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
/openbmc/u-boot/include/environment/ti/
H A Ddfu.h13 "boot part 0 1;" \
14 "rootfs part 0 2;" \
15 "MLO fat 0 1;" \
16 "MLO.raw raw 0x100 0x100;" \
17 "u-boot.img.raw raw 0x300 0x1000;" \
18 "u-env.raw raw 0x1300 0x200;" \
19 "spl-os-args.raw raw 0x1500 0x200;" \
20 "spl-os-image.raw raw 0x1700 0x6900;" \
21 "spl-os-args fat 0 1;" \
22 "spl-os-image fat 0 1;" \
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-lmu5000.dts20 reg = <0x20000000 0x4000000>;
28 main_clock: clock@0 {
43 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
48 reg = <0x3 0x0 0x800000>;
62 kernel@0 {
64 reg = <0x0 0x400000>;
69 reg = <0x400000 0x3C00000>;
74 reg = <0x4000000 0x2000000>;
79 reg = <0x6000000 0x2000000>;
107 pinctrl-0 = <&pinctrl_ssc0_tx>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/reserved-memory/
H A Dshared-dma-pool.yaml82 size = <0x4000000>;
83 alignment = <0x2000>;
88 reg = <0x78000000 0x800000>;
93 reg = <0x50000000 0x4000000>;
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dtlb.c10 /* TLB 0 - for temp stack in cache */
11 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
12 MAS3_SX|MAS3_SW|MAS3_SR, 0,
13 0, 0, BOOKE_PAGESZ_4K, 0),
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
20 MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-sev-kit.dts42 reg = <0x0 0x80000000 0x0 0x2000000>;
47 reg = <0x0 0xc4000000 0x0 0x4000000>;
52 reg = <0x0 0xd4000000 0x0 0x4000000>;
58 reg = <0x10 0x0 0x0 0x76000000>;
/openbmc/u-boot/include/configs/
H A Dtopic_miami.h19 #define CONFIG_ENV_SIZE 0x8000
21 #define CONFIG_ENV_OFFSET 0x80000
26 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
46 #define CONFIG_SYS_MEMTEST_START 0
48 #define CONFIG_SYS_MEMTEST_END 0x18000000
58 "i2c mw 41 1 fe && i2c mw 41 1 ff\0" \
61 "if load usb 0 0x1900000 ${bootscript}; then "\
62 "source 0x1900000; fi; " \
63 "load usb 0 ${kernel_addr} ${kernel_image} && " \
64 "load usb 0 ${devicetree_addr} ${devicetree_image} && " \
[all …]
H A Dx86-common.h34 #define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
40 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
54 "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
66 #define CONFIG_SYS_MEMTEST_START 0x00100000
67 #define CONFIG_SYS_MEMTEST_END 0x01000000
68 #define CONFIG_SYS_LOAD_ADDR 0x20000000
76 #define CONFIG_SYS_MALLOC_LEN 0x200000
84 #define CONFIG_ENV_SIZE 0x01000
102 #define CONFIG_LOADADDR 0x1000000
103 #define CONFIG_RAMDISK_ADDR 0x4000000
[all …]
/openbmc/u-boot/board/sbc8548/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 0, 0, BOOKE_PAGESZ_4K, 0),
17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 MAS3_SX|MAS3_SW|MAS3_SR, 0,
20 0, 0, BOOKE_PAGESZ_4K, 0),
21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 MAS3_SX|MAS3_SW|MAS3_SR, 0,
24 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt25 first address cell and it may accept values 0..N-1
76 it can be in range [0-3]. For compatible
105 Minimum value is 1 (0 treated as 1).
110 Minimum value is 1 (0 treated as 1).
117 Minimum value is 1 (0 treated as 1).
122 Minimum value is 1 (0 treated as 1).
127 Minimum value is 1 (0 treated as 1).
134 Minimum value is 1 (0 treated as 1).
145 clocks = <&clkaemif 0>;
148 reg = <0x21000A00 0x00000100>;
[all …]
/openbmc/linux/drivers/net/ethernet/atheros/atlx/
H A Datlx.h23 #define SPEED_0 0xffff
30 #define MEDIA_TYPE_AUTO_SENSOR 0
33 #define REG_PM_CTRLSTAT 0x44
35 #define REG_PCIE_CAP_LIST 0x58
37 #define REG_VPD_CAP 0x6C
38 #define VPD_CAP_ID_MASK 0xFF
39 #define VPD_CAP_ID_SHIFT 0
40 #define VPD_CAP_NEXT_PTR_MASK 0xFF
42 #define VPD_CAP_VPD_ADDR_MASK 0x7FFF
44 #define VPD_CAP_VPD_FLAG 0x80000000
[all …]
/openbmc/linux/arch/arm/boot/dts/sigmastar/
H A Dmstar-infinity3-msc313e.dtsi12 reg = <0x20000000 0x4000000>;
H A Dmstar-infinity-msc313.dtsi12 reg = <0x20000000 0x4000000>;

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