| /openbmc/linux/Documentation/sound/cards/ |
| H A D | serial-u16550.rst | 7 * 0 - Roland Soundcanvas support (default)
28 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 speed=115200
34 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 outs=4
45 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 adaptor=1 \
56 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 adaptor=2
73 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 adaptor=3
|
| /openbmc/linux/arch/x86/boot/ |
| H A D | early_serial_console.c | 8 #define DEFAULT_SERIAL_PORT 0x3f8 /* ttyS0 */
10 #define DLAB 0x80
12 #define TXR 0 /* Transmit register (WRITE) */
13 #define RXR 0 /* Receive register (READ) */
21 #define DLL 0 /* Divisor Latch Low */
31 outb(0x3, port + LCR); /* 8n1 */ in early_serial_init()
32 outb(0, port + IER); /* no interrupt */ in early_serial_init()
33 outb(0, port + FCR); /* no fifo */ in early_serial_init()
34 outb(0x3, port + MCR); /* DTR + RTS */ in early_serial_init()
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
[all …]
|
| /openbmc/linux/arch/mips/loongson2ef/common/ |
| H A D | uart_base.c | 25 loongson_uart_base = LOONGSON_PCIIO_BASE + 0x3f8; in prom_init_loongson_uart_base()
29 loongson_uart_base = LOONGSON_PCIIO_BASE + 0x2f8; in prom_init_loongson_uart_base()
37 loongson_uart_base = LOONGSON_LIO1_BASE + 0x3f8; in prom_init_loongson_uart_base()
42 setup_8250_early_printk_port(_loongson_uart_base, 0, 1024); in prom_init_loongson_uart_base()
|
| /openbmc/linux/arch/arm/mach-mediatek/ |
| H A D | platsmp.c | 17 #define MTK_SMP_REG_SIZE 0x1000
27 0x80002000, 0x3fc,
28 { 0x534c4131, 0x4c415332, 0x41534c33 },
29 { 0x3f8, 0x3f8, 0x3f8 },
33 0x10002000, 0x34,
34 { 0x534c4131, 0x4c415332, 0x41534c33 },
35 { 0x38, 0x3c, 0x40 },
39 0x10202000, 0x34,
40 { 0x534c4131, 0x4c415332, 0x41534c33 },
41 { 0x38, 0x3c, 0x40 },
[all …]
|
| /openbmc/u-boot/arch/mips/include/asm/ |
| H A D | malta.h | 10 #define MALTA_GT_BASE 0x1be00000
11 #define MALTA_GT_PCIIO_BASE 0x18000000
12 #define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8)
14 #define MALTA_MSC01_BIU_BASE 0x1bc80000
15 #define MALTA_MSC01_PCI_BASE 0x1bd00000
16 #define MALTA_MSC01_PBC_BASE 0x1bd40000
17 #define MALTA_MSC01_IP1_BASE 0x1bc00000
18 #define MALTA_MSC01_IP1_SIZE 0x00400000
19 #define MALTA_MSC01_IP2_BASE1 0x10000000
20 #define MALTA_MSC01_IP2_SIZE1 0x08000000
[all …]
|
| /openbmc/u-boot/board/intel/cougarcanyon2/ |
| H A D | cougarcanyon2.c | 16 #define SIO1007_RUNTIME_IOPORT 0x180
33 (SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN); in board_early_init_f()
37 /* Enable legacy serial port at 0x3f8 */ in board_early_init_f()
38 sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ); in board_early_init_f()
40 /* Enable SIO1007 runtime I/O port at 0x180 */ in board_early_init_f()
45 * port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007. in board_early_init_f()
48 sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT, in board_early_init_f()
50 sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1); in board_early_init_f()
52 return 0; in board_early_init_f()
|
| /openbmc/linux/arch/arm/mach-footbridge/ |
| H A D | isa.c | 16 [0] = {
17 .start = 0x70,
18 .end = 0x73,
36 [0] = {
37 .start = 0x3f8,
38 .end = 0x3ff,
42 .start = 0x2f8,
43 .end = 0x2ff,
50 .iobase = 0x3f8,
53 .regshift = 0,
[all …]
|
| /openbmc/linux/Documentation/arch/ia64/ |
| H A D | serial.rst | 24 legacy COM port addresses (I/O ports 0x3f8 and 0x2f8), so
44 builtin 0xff5e0000 ttyS0 ttyS1 ttyS0
45 MP UPS 0xf8031000 ttyS1 ttyS2 ttyS1
46 MP Console 0xf8030000 ttyS2 ttyS0 ttyS2
47 MP 2 0xf8030010 ttyS3 ttyS3 ttyS3
48 MP 3 0xf8030038 ttyS4 ttyS4 ttyS4
89 this if the user supplies an argument like "console=uart,io,0x3f8",
125 devices. Use "console=uart,io,0x3f8" (or appropriate
|
| /openbmc/qemu/tests/migration/i386/ |
| H A D | a-b-bootblock.S | 14 #define ACPI_ENABLE 0xf1
15 #define ACPI_PORT_SMI_CMD 0xb2
16 #define ACPI_PM_BASE 0x600
19 #define ACPI_SCI_ENABLE 0x0001
20 #define ACPI_SLEEP_TYPE 0x0400
21 #define ACPI_SLEEP_ENABLE 0x2000
31 .org 0x7c00
36 start: # at 0x7c00 ?
41 data32 ljmp $8,$0x7c20
43 .org 0x7c20
[all …]
|
| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
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| /openbmc/linux/drivers/media/common/b2c2/ |
| H A D | flexcop-eeprom.c | 9 #if 0
13 return flex_i2c_write(adapter, 0x20000000, 0x50, addr, buf, len);
21 for (i = 0; i < retries; i++) {
27 return 0;
38 return 0;
41 wbuf[16] = 0;
42 wbuf[17] = 0;
43 wbuf[18] = 0;
45 return eeprom_lrc_write(adapter, 0x3e4, 20, wbuf, rbuf, 4);
53 return 0;
[all …]
|
| /openbmc/openbmc/meta-phosphor/recipes-phosphor/console/obmc-console/ |
| H A D | obmc-console.conf | 1 lpc-address = 0x3f8
|
| /openbmc/openbmc/meta-ibm/recipes-phosphor/console/obmc-console/witherspoon-tacoma/ |
| H A D | server.ttyVUART0.conf | 1 lpc-address = 0x3f8
|
| /openbmc/openbmc/meta-ibm/recipes-phosphor/console/obmc-console/sbp1/ |
| H A D | server.ttyVUART0.conf | 1 lpc-address = 0x3f8
|
| /openbmc/openbmc/meta-ibm/recipes-phosphor/console/obmc-console/p10bmc/ |
| H A D | server.ttyVUART0.conf | 1 lpc-address = 0x3f8
|
| /openbmc/openbmc/meta-yadro/meta-nicole/recipes-phosphor/console/obmc-console/ |
| H A D | obmc-console.conf | 1 lpc-address = 0x3f8
|
| /openbmc/openbmc/meta-ibm/meta-palmetto/recipes-phosphor/console/obmc-console/ |
| H A D | obmc-console.conf | 1 lpc-address = 0x3f8
|
| /openbmc/openbmc/meta-ibm/meta-romulus/recipes-phosphor/console/obmc-console/ |
| H A D | obmc-console.conf | 1 lpc-address = 0x3f8
|
| /openbmc/openbmc/meta-ibm/recipes-phosphor/console/obmc-console/ibm-ac-server/ |
| H A D | server.ttyVUART0.conf | 1 lpc-address = 0x3f8
|
| /openbmc/openbmc/meta-ingrasys/meta-zaius/recipes-phosphor/console/obmc-console/ |
| H A D | obmc-console.conf | 1 lpc-address = 0x3f8
|
| /openbmc/openbmc/meta-ibm/recipes-phosphor/console/obmc-console/system1/ |
| H A D | server.ttyVUART0.conf | 1 lpc-address = 0x3f8
|
| /openbmc/u-boot/arch/x86/dts/ |
| H A D | serial.dtsi | 5 reg = <0x3f8 8>;
6 reg-shift = <0>;
|
| /openbmc/obmc-console/conf/ |
| H A D | server.ttyVUART0.conf.in | 1 lpc-address = 0x3f8
|
| /openbmc/openbmc/meta-amd/meta-common/recipes-phosphor/console/obmc-console/ |
| H A D | server.ttyVUART0.conf | 1 lpc-address = 0x3f8
|
| /openbmc/u-boot/arch/x86/include/asm/ |
| H A D | ibmpc.h | 12 #define MASTER_PIC 0x20
13 #define PIT_BASE 0x40
14 #define KBDDATA 0x60
15 #define SYSCTLB 0x62
16 #define KBDCMD 0x64
17 #define SYSCTLA 0x92
18 #define SLAVE_PIC 0xa0
20 #define UART0_BASE 0x3f8
21 #define UART1_BASE 0x2f8
|