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/openbmc/linux/arch/xtensa/boot/dts/
H A Dkc705.dts9 …earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw…
11 memory@0 {
13 reg = <0x00000000 0x38000000>;
25 size = <0x04000000>;
26 alignment = <0x2000>;
27 alloc-ranges = <0x00000000 0x20000000>;
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Drcar-pci-host.yaml115 reg = <0 0xfe000000 0 0x80000>;
118 bus-range = <0x00 0xff>;
120 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
121 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
122 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
123 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
124 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
125 <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
130 interrupt-map-mask = <0 0 0 0>;
131 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
/openbmc/u-boot/board/cadence/xtfpga/
H A DKconfig33 default 0x04000000 if XTFPGA_LX60
34 default 0x03000000 if XTFPGA_LX110
35 default 0x06000000 if XTFPGA_LX200
36 default 0x18000000 if XTFPGA_ML605
37 default 0x38000000 if XTFPGA_KC705
/openbmc/u-boot/arch/xtensa/dts/
H A Dkc705.dts8 …bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root…
11 memory@0 {
13 reg = <0x00000000 0x38000000>;
/openbmc/u-boot/arch/arm/include/asm/arch-bcm281xx/
H A Dsysmap.h8 #define BSC1_BASE_ADDR 0x3e016000
9 #define BSC2_BASE_ADDR 0x3e017000
10 #define BSC3_BASE_ADDR 0x3e018000
11 #define DWDMA_AHB_BASE_ADDR 0x38100000
12 #define ESUB_CLK_BASE_ADDR 0x38000000
13 #define ESW_CONTRL_BASE_ADDR 0x38200000
14 #define GPIO2_BASE_ADDR 0x35003000
15 #define HSOTG_BASE_ADDR 0x3f120000
16 #define HSOTG_CTRL_BASE_ADDR 0x3f130000
17 #define KONA_MST_CLK_BASE_ADDR 0x3f001000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dst,stm32-rproc.yaml168 reg = <0x10000000 0x40000>,
169 <0x30000000 0x40000>,
170 <0x38000000 0x10000>;
174 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
175 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
176 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
182 reg = <0x10000000 0x40000>,
183 <0x30000000 0x40000>,
184 <0x38000000 0x10000>;
188 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
[all …]
/openbmc/u-boot/board/d-link/dns325/
H A Ddns325.h16 #define DNS325_OE_LOW 0x00000000
17 #define DNS325_OE_HIGH 0x00039604
18 #define DNS325_OE_VAL_LOW 0x38000000 /* disable leds */
19 #define DNS325_OE_VAL_HIGH 0x00000800 /* disable leds */
/openbmc/u-boot/arch/arm/dts/
H A Dr8a7796-m3ulcb.dts20 reg = <0x0 0x48000000 0x0 0x38000000>;
25 reg = <0x6 0x00000000 0x0 0x40000000>;
37 clock-names = "du.0", "du.1", "du.2", "lvds.0",
38 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a7795-h3ulcb.dts14 model = "Renesas H3ULCB board based on r8a7795 ES2.0+";
20 reg = <0x0 0x48000000 0x0 0x38000000>;
25 reg = <0x5 0x00000000 0x0 0x40000000>;
30 reg = <0x6 0x00000000 0x0 0x40000000>;
35 reg = <0x7 0x00000000 0x0 0x40000000>;
49 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
50 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
H A Dethernut5.dts20 reg = <0x20000000 0x08000000>;
64 gpios = <0
66 0
69 root@0 {
71 reg = <0x0 0x08000000>;
76 reg = <0x08000000 0x38000000>;
86 i2c-gpio-0 {
88 #size-cells = <0>;
93 reg = <0x51>;
H A Dr8a77990-ebisu.dts29 reg = <0x0 0x48000000 0x0 0x38000000>;
34 pinctrl-0 = <&avb_pins>;
41 phy0: ethernet-phy@0 {
43 reg = <0>;
91 pinctrl-0 = <&usb0_pins>;
98 pinctrl-0 = <&usb30_pins>;
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77960-ulcb.dts20 reg = <0x0 0x48000000 0x0 0x38000000>;
25 reg = <0x6 0x00000000 0x0 0x40000000>;
36 clock-names = "du.0", "du.1", "du.2",
37 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a77951-salvator-x.dts3 * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0
19 reg = <0x0 0x48000000 0x0 0x38000000>;
24 reg = <0x5 0x00000000 0x0 0x40000000>;
29 reg = <0x6 0x00000000 0x0 0x40000000>;
34 reg = <0x7 0x00000000 0x0 0x40000000>;
47 clock-names = "du.0", "du.1", "du.2", "du.3",
48 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
H A Dr8a77951-ulcb.dts3 * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board with R-Car H3 ES2.0+
20 reg = <0x0 0x48000000 0x0 0x38000000>;
25 reg = <0x5 0x00000000 0x0 0x40000000>;
30 reg = <0x6 0x00000000 0x0 0x40000000>;
35 reg = <0x7 0x00000000 0x0 0x40000000>;
48 clock-names = "du.0", "du.1", "du.2", "du.3",
49 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
H A Dr8a77951-salvator-xs.dts3 * Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES2.0+
19 reg = <0x0 0x48000000 0x0 0x38000000>;
24 reg = <0x5 0x00000000 0x0 0x40000000>;
29 reg = <0x6 0x00000000 0x0 0x40000000>;
34 reg = <0x7 0x00000000 0x0 0x40000000>;
47 clock-names = "du.0", "du.1", "du.2", "du.3",
48 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
H A Dr8a779m1-ulcb.dts24 reg = <0x0 0x48000000 0x0 0x38000000>;
29 reg = <0x5 0x00000000 0x0 0x40000000>;
34 reg = <0x6 0x00000000 0x0 0x40000000>;
39 reg = <0x7 0x00000000 0x0 0x40000000>;
52 clock-names = "du.0", "du.1", "du.2", "du.3",
53 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
H A Dr8a779m1-salvator-xs.dts23 reg = <0x0 0x48000000 0x0 0x38000000>;
28 reg = <0x5 0x00000000 0x0 0x40000000>;
33 reg = <0x6 0x00000000 0x0 0x40000000>;
38 reg = <0x7 0x00000000 0x0 0x40000000>;
51 clock-names = "du.0", "du.1", "du.2", "du.3",
52 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dhpe,gxp-spifi.yaml41 reg = <0x200 0x80>, <0xc000 0x100>, <0x38000000 0x800000>;
45 #size-cells = <0>;
47 flash@0 {
48 reg = <0>;
/openbmc/u-boot/board/emulation/qemu-arm/
H A Dqemu-arm.c18 .virt = 0x00000000UL,
19 .phys = 0x00000000UL,
20 .size = 0x08000000UL,
25 .virt = 0x08000000UL,
26 .phys = 0x08000000UL,
27 .size = 0x38000000,
33 .virt = 0x40000000UL,
34 .phys = 0x40000000UL,
40 .virt = 0x4010000000ULL,
41 .phys = 0x4010000000ULL,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/stm32/
H A Dst,mlahb.yaml61 reg = <0x10000000 0x40000>;
63 dma-ranges = <0x00000000 0x38000000 0x10000>,
64 <0x10000000 0x10000000 0x60000>,
65 <0x30000000 0x30000000 0x60000>;
68 reg = <0x10000000 0x40000>;
/openbmc/linux/arch/xtensa/configs/
H A Dxip_kc705_defconfig23 CONFIG_XIP_DATA_ADDR=0xd0000000
24 CONFIG_KERNEL_VIRTUAL_ADDRESS=0xe6000000
25 CONFIG_KERNEL_LOAD_ADDRESS=0xf6000000
30 …arlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw …
H A Dgeneric_kc705_defconfig30 …arlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw …
H A Daudio_kc705_defconfig31 …arlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw …
/openbmc/linux/arch/sparc/include/asm/
H A Dfbio.h10 #define CG6_FBC 0x70000000
11 #define CG6_TEC 0x70001000
12 #define CG6_BTREGS 0x70002000
13 #define CG6_FHC 0x70004000
14 #define CG6_THC 0x70005000
15 #define CG6_ROM 0x70006000
16 #define CG6_RAM 0x70016000
17 #define CG6_DHC 0x80000000
19 #define CG3_MMAP_OFFSET 0x4000000
22 #define TCX_RAM8BIT 0x00000000
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dethernut5.dts19 reg = <0x20000000 0x08000000>;
39 timer@0 {
41 reg = <0>, <1>;
74 pinctrl-0 = <&pinctrl_nand_cs>;
78 reg = <0x3 0x0 0x800000>;
90 root@0 {
92 reg = <0x0 0x08000000>;
97 reg = <0x08000000 0x38000000>;
110 i2c-gpio-0 {
115 reg = <0x51>;

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