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/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/openbmc/linux/drivers/s390/cio/
H A Ddevice_id.c31 * diag210_to_senseid - convert diag 0x210 data to sense id information
33 * @diag: diag 0x210 data
35 * Return 0 on success, non-zero otherwise.
42 { 0x08, 0x01, 0x3480 }, in diag210_to_senseid()
43 { 0x08, 0x02, 0x3430 }, in diag210_to_senseid()
44 { 0x08, 0x10, 0x3420 }, in diag210_to_senseid()
45 { 0x08, 0x42, 0x3424 }, in diag210_to_senseid()
46 { 0x08, 0x44, 0x9348 }, in diag210_to_senseid()
47 { 0x08, 0x81, 0x3490 }, in diag210_to_senseid()
48 { 0x08, 0x82, 0x3422 }, in diag210_to_senseid()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-stm32/
H A Dstm32f.h10 #define STM32_PERIPH_BASE 0x40000000UL
12 #define STM32_APB2_PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
13 #define STM32_AHB1_PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000)
15 #define STM32_SYSCFG_BASE (STM32_APB2_PERIPH_BASE + 0x3800)
16 #define STM32_FLASH_CNTL_BASE (STM32_AHB1_PERIPH_BASE + 0x3C00)
/openbmc/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_dev.h9 #define PCI_VENDOR_ID_CORIGINE 0x1da8
10 #define PCI_DEVICE_ID_NFP3800 0x3800
11 #define PCI_DEVICE_ID_NFP4000 0x4000
12 #define PCI_DEVICE_ID_NFP5000 0x5000
13 #define PCI_DEVICE_ID_NFP6000 0x6000
14 #define PCI_DEVICE_ID_NFP3800_VF 0x3803
15 #define PCI_DEVICE_ID_NFP6000_VF 0x6003
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dmc5.c42 DBGI_MODE_MBUS = 0,
47 #define IDT_CMD_READ 0
53 #define IDT_LAR_ADR0 0x180006
54 #define IDT_LAR_MODE144 0xffff0000
57 #define IDT_SCR_ADR0 0x180000
58 #define IDT_SSR0_ADR0 0x180002
59 #define IDT_SSR1_ADR0 0x180004
62 #define IDT_GMR_BASE_ADR0 0x180020
65 #define IDT_DATARY_BASE_ADR0 0
66 #define IDT_MSKARY_BASE_ADR0 0x80000
[all …]
/openbmc/linux/drivers/staging/media/atomisp/i2c/
H A Dov2722.h38 #define I2C_MSG_LENGTH 0x2
47 * bits 31-16: numerator, bits 15-0: denominator
49 #define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064
53 * bits 31-16: numerator, bits 15-0: denominator
55 #define OV2722_F_NUMBER_DEFAULT 0x1a000a
62 * bits 7-0: min f-number denominator
64 #define OV2722_F_NUMBER_RANGE 0x1a0a1a0a
65 #define OV2720_ID 0x2720
66 #define OV2722_ID 0x2722
68 #define OV2722_FINE_INTG_TIME_MIN 0
[all …]
/openbmc/linux/drivers/staging/media/atomisp/i2c/ov5693/
H A Dov5693.h38 #define ENABLE_NON_PREVIEW 0
43 #define I2C_MSG_LENGTH 0x2
54 #define OV5693_READ_MODE_BINNING_ON 0x0400
55 #define OV5693_READ_MODE_BINNING_OFF 0x00
58 #define OV5693_MAX_EXPOSURE_VALUE 0xFFF1
59 #define OV5693_MAX_GAIN_VALUE 0xFF
63 * bits 31-16: numerator, bits 15-0: denominator
65 #define OV5693_FOCAL_LENGTH_DEFAULT 0x1B70064
69 * bits 31-16: numerator, bits 15-0: denominator
71 #define OV5693_F_NUMBER_DEFAULT 0x18000a
[all …]
/openbmc/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_xgmac.h12 #define X2_BLOCK_ETH_MAC_CSR_OFFSET 0x3000
13 #define BLOCK_AXG_MAC_OFFSET 0x0800
14 #define BLOCK_AXG_STATS_OFFSET 0x0800
15 #define BLOCK_AXG_MAC_CSR_OFFSET 0x2000
16 #define BLOCK_PCS_OFFSET 0x3800
18 #define XGENET_CONFIG_REG_ADDR 0x20
19 #define XGENET_SRST_ADDR 0x00
20 #define XGENET_CLKEN_ADDR 0x08
22 #define CSR_CLK BIT(0)
29 #define CSR_RST BIT(0)
[all …]
/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dqspi.h14 u16 mr; /* 0x00 Mode */
16 u16 dlyr; /* 0x04 Delay */
18 u16 wr; /* 0x08 Wrap */
20 u16 ir; /* 0x0C Interrupt */
22 u16 ar; /* 0x10 Address */
24 u16 dr; /* 0x14 Data */
29 #define QSPI_QMR_MSTR (0x8000)
30 #define QSPI_QMR_DOHIE (0x4000)
31 #define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
32 #define QSPI_QMR_BITS_MASK (0xC3FF)
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A Dgt215.c36 { 0x0001, "ILLEGAL_MTHD" },
37 { 0x0002, "INVALID_ENUM" },
38 { 0x0003, "INVALID_BITFIELD" },
47 const u32 base = subdev->inst * 0x1000; in gt215_ce_intr()
48 u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff; in gt215_ce_intr()
49 u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16; in gt215_ce_intr()
50 u32 mthd = (addr & 0x07ff) << 2; in gt215_ce_intr()
51 u32 subc = (addr & 0x3800) >> 11; in gt215_ce_intr()
52 u32 data = nvkm_rd32(device, 0x104044 + base); in gt215_ce_intr()
59 chan ? chan->inst->addr : 0, in gt215_ce_intr()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/
H A Dg98.c35 { 0x0000, "ILLEGAL_MTHD" },
36 { 0x0001, "INVALID_BITFIELD" },
37 { 0x0002, "INVALID_ENUM" },
38 { 0x0003, "QUERY" },
47 u32 ssta = nvkm_rd32(device, 0x087040) & 0x0000ffff; in g98_sec_intr()
48 u32 addr = nvkm_rd32(device, 0x087040) >> 16; in g98_sec_intr()
49 u32 mthd = (addr & 0x07ff) << 2; in g98_sec_intr()
50 u32 subc = (addr & 0x3800) >> 11; in g98_sec_intr()
51 u32 data = nvkm_rd32(device, 0x087044); in g98_sec_intr()
58 chan ? chan->inst->addr : 0, in g98_sec_intr()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dov5695.c30 #define CHIP_ID 0x005695
31 #define OV5695_REG_CHIP_ID 0x300a
33 #define OV5695_REG_CTRL_MODE 0x0100
34 #define OV5695_MODE_SW_STANDBY 0x0
35 #define OV5695_MODE_STREAMING BIT(0)
37 #define OV5695_REG_EXPOSURE 0x3500
40 #define OV5695_VTS_MAX 0x7fff
42 #define OV5695_REG_ANALOG_GAIN 0x3509
43 #define ANALOG_GAIN_MIN 0x10
44 #define ANALOG_GAIN_MAX 0xf8
[all …]
H A Dov13b10.c19 #define OV13B10_REG_MODE_SELECT 0x0100
20 #define OV13B10_MODE_STANDBY 0x00
21 #define OV13B10_MODE_STREAMING 0x01
23 #define OV13B10_REG_SOFTWARE_RST 0x0103
24 #define OV13B10_SOFTWARE_RST 0x01
27 #define OV13B10_REG_CHIP_ID 0x300a
28 #define OV13B10_CHIP_ID 0x560d42
31 #define OV13B10_REG_VTS 0x380e
32 #define OV13B10_VTS_30FPS 0x0c7c
33 #define OV13B10_VTS_60FPS 0x063e
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dbrcmu_d11.h20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
23 #define BRCMU_CHSPEC_CH_MASK 0x00ff
24 #define BRCMU_CHSPEC_CH_SHIFT 0
25 #define BRCMU_CHSPEC_CHL_MASK 0x000f
26 #define BRCMU_CHSPEC_CHL_SHIFT 0
27 #define BRCMU_CHSPEC_CHH_MASK 0x00f0
36 #define BRCMU_CHSPEC_D11N_SB_MASK 0x0300
38 #define BRCMU_CHSPEC_D11N_SB_L 0x0100 /* control lower */
39 #define BRCMU_CHSPEC_D11N_SB_U 0x0200 /* control upper */
[all …]
/openbmc/linux/arch/x86/math-emu/
H A Dstatus_w.h22 #define SW_Backward Const__(0x8000) /* backward compatibility */
23 #define SW_C3 Const__(0x4000) /* condition bit 3 */
24 #define SW_Top Const__(0x3800) /* top of stack */
26 #define SW_C2 Const__(0x0400) /* condition bit 2 */
27 #define SW_C1 Const__(0x0200) /* condition bit 1 */
28 #define SW_C0 Const__(0x0100) /* condition bit 0 */
29 #define SW_Summary Const__(0x0080) /* exception summary */
30 #define SW_Stack_Fault Const__(0x0040) /* stack fault */
31 #define SW_Precision Const__(0x0020) /* loss of precision */
32 #define SW_Underflow Const__(0x0010) /* underflow */
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-broadwell/
H A Dspi.h16 #define SPIBAR_OFFSET 0x3800
20 #define SPIBAR_SSFC 0x91
21 #define SPIBAR_FDOC 0xb0
22 #define SPIBAR_FDOD 0xb4
24 #define SPIBAR_PREOP 0x94
25 #define SPIBAR_OPTYPE 0x96
26 #define SPIBAR_OPMENU_LOWER 0x98
27 #define SPIBAR_OPMENU_UPPER 0x9c
29 #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
30 #define SPI_OPTYPE_0 0x01 /* Write, no address */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h12 #define REGS_AHB0_BASE 0x01C00000
13 #define REGS_AHB1_BASE 0x00800000
14 #define REGS_AHB2_BASE 0x03000000
15 #define REGS_APB0_BASE 0x06000000
16 #define REGS_APB1_BASE 0x07000000
17 #define REGS_RCPUS_BASE 0x08000000
19 #define SUNXI_SRAM_D_BASE 0x08100000
22 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
23 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
25 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
/openbmc/linux/sound/soc/codecs/
H A Drt700.h30 #define RT700_AUDIO_FUNCTION_GROUP 0x01
31 #define RT700_DAC_OUT1 0x02
32 #define RT700_DAC_OUT2 0x03
33 #define RT700_ADC_IN1 0x09
34 #define RT700_ADC_IN2 0x08
35 #define RT700_DMIC1 0x12
36 #define RT700_DMIC2 0x13
37 #define RT700_SPK_OUT 0x14
38 #define RT700_MIC2 0x19
39 #define RT700_LINE1 0x1a
[all …]
H A Drt715.h30 #define RT715_AUDIO_FUNCTION_GROUP 0x01
31 #define RT715_MIC_ADC 0x07
32 #define RT715_LINE_ADC 0x08
33 #define RT715_MIX_ADC 0x09
34 #define RT715_DMIC1 0x12
35 #define RT715_DMIC2 0x13
36 #define RT715_MIC1 0x18
37 #define RT715_MIC2 0x19
38 #define RT715_LINE1 0x1a
39 #define RT715_LINE2 0x1b
[all …]
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a23.c35 .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
36 .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
40 .mr3 = 0,
42 .tpr0 = 0x2ab83def,
43 .tpr1 = 0x18082356,
44 .tpr2 = 0x00034156,
45 .tpr3 = 0x448c5533,
46 .tpr4 = 0x08010d00,
47 .tpr5 = 0x0340b20f,
48 .tpr6 = 0x20d118cc,
[all …]
/openbmc/linux/arch/m68k/ifpsp060/src/
H A Dilsp.S36 short 0x0000
38 short 0x0000
41 short 0x0000
43 short 0x0000
46 short 0x0000
48 short 0x0000
50 short 0x0000
52 short 0x0000
54 short 0x0000
56 short 0x0000
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dmc44s803_priv.h14 SPI or I2C Address : 0xc0-0xc6
28 0A | LNA AGC
29 0B | Data Register Address
30 0C | Regulator Test
31 0D | VCO Test
32 0E | LNA Gain/Input Power
33 0F | ID Bits
41 #define MC44S803_REG_POWER 0
51 #define MC44S803_REG_LNAAGC 0x0A
52 #define MC44S803_REG_DATAREG 0x0B
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/openbmc/u-boot/include/configs/
H A Dls1088ardb.h12 #define CONFIG_SYS_MMC_ENV_DEV 0
14 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
15 #define CONFIG_ENV_OFFSET 0x500000
18 #define CONFIG_ENV_SECT_SIZE 0x40000
21 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
22 #define CONFIG_ENV_SECT_SIZE 0x40000
25 #define CONFIG_SYS_MMC_ENV_DEV 0
26 #define CONFIG_ENV_SIZE 0x2000
29 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
30 #define CONFIG_ENV_SECT_SIZE 0x20000
[all …]

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