Home
last modified time | relevance | path

Searched +full:0 +full:x3600 (Results 1 – 25 of 81) sorted by relevance

1234

/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dqcom,spmi-iadc.yaml16 (channel 0). When using an external resistor it is to be described by
55 #size-cells = <0>;
58 reg = <0x3600>;
59 interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
/openbmc/linux/drivers/staging/media/atomisp/i2c/
H A Dov2722.h38 #define I2C_MSG_LENGTH 0x2
47 * bits 31-16: numerator, bits 15-0: denominator
49 #define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064
53 * bits 31-16: numerator, bits 15-0: denominator
55 #define OV2722_F_NUMBER_DEFAULT 0x1a000a
62 * bits 7-0: min f-number denominator
64 #define OV2722_F_NUMBER_RANGE 0x1a0a1a0a
65 #define OV2720_ID 0x2720
66 #define OV2722_ID 0x2722
68 #define OV2722_FINE_INTG_TIME_MIN 0
[all …]
/openbmc/linux/sound/soc/codecs/
H A Drt700.h30 #define RT700_AUDIO_FUNCTION_GROUP 0x01
31 #define RT700_DAC_OUT1 0x02
32 #define RT700_DAC_OUT2 0x03
33 #define RT700_ADC_IN1 0x09
34 #define RT700_ADC_IN2 0x08
35 #define RT700_DMIC1 0x12
36 #define RT700_DMIC2 0x13
37 #define RT700_SPK_OUT 0x14
38 #define RT700_MIC2 0x19
39 #define RT700_LINE1 0x1a
[all …]
H A Drt715.h30 #define RT715_AUDIO_FUNCTION_GROUP 0x01
31 #define RT715_MIC_ADC 0x07
32 #define RT715_LINE_ADC 0x08
33 #define RT715_MIX_ADC 0x09
34 #define RT715_DMIC1 0x12
35 #define RT715_DMIC2 0x13
36 #define RT715_MIC1 0x18
37 #define RT715_MIC2 0x19
38 #define RT715_LINE1 0x1a
39 #define RT715_LINE2 0x1b
[all …]
H A Drt711.h32 #define RT711_AUDIO_FUNCTION_GROUP 0x01
33 #define RT711_DAC_OUT2 0x03
34 #define RT711_ADC_IN1 0x09
35 #define RT711_ADC_IN2 0x08
36 #define RT711_DMIC1 0x12
37 #define RT711_DMIC2 0x13
38 #define RT711_MIC2 0x19
39 #define RT711_LINE1 0x1a
40 #define RT711_LINE2 0x1b
41 #define RT711_BEEP 0x1d
[all …]
/openbmc/u-boot/fs/ext4/
H A Dcrc16.c13 /** CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1) */
15 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
16 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
17 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
18 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
19 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
20 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
21 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
22 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
23 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/linux/lib/
H A Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/u-boot/fs/ubifs/
H A Dcrc16.c11 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
13 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
14 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
15 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
16 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
17 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
18 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
19 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
20 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
21 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dpm8226.dtsi11 polling-delay = <0>;
38 pm8226_0: pm8226@0 {
40 reg = <0x0 SPMI_USID>;
42 #size-cells = <0>;
46 reg = <0x800>;
50 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
58 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
67 reg = <0x1000>;
68 interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
69 <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
[all …]
H A Dpm8941.dtsi11 polling-delay = <0>;
39 pm8941_0: pm8941@0 {
41 reg = <0x0 SPMI_USID>;
43 #size-cells = <0>;
47 reg = <0x6000>,
48 <0x6100>;
50 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
55 reg = <0x800>;
59 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
66 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/openbmc/linux/drivers/mfd/
H A Dsi476x-prop.c25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array()
38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range()
49 0x0000, in si476x_core_is_valid_property_a10()
50 0x0500, 0x0501, in si476x_core_is_valid_property_a10()
51 0x0600, in si476x_core_is_valid_property_a10()
52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10()
53 0x0718, in si476x_core_is_valid_property_a10()
54 0x1207, 0x1208, in si476x_core_is_valid_property_a10()
55 0x2007, in si476x_core_is_valid_property_a10()
56 0x2300, in si476x_core_is_valid_property_a10()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Domap.h15 #define SMX_APE_BASE 0x68000000
18 #define OMAP34XX_GPMC_BASE 0x6E000000
21 #define OMAP34XX_SMS_BASE 0x6C000000
24 #define OMAP34XX_SDRC_BASE 0x6D000000
29 #define OMAP34XX_CORE_L4_IO_BASE 0x48000000
30 #define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
31 #define OMAP34XX_ID_L4_IO_BASE 0x4830A200
32 #define OMAP34XX_L4_PER 0x49000000
36 #define OMAP34XX_DMA4_BASE 0x48056000
39 #define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dov5647.c42 #define MIPI_CTRL00_CLOCK_LANE_DISABLE BIT(0)
44 #define OV5647_SW_STANDBY 0x0100
45 #define OV5647_SW_RESET 0x0103
46 #define OV5647_REG_CHIPID_H 0x300a
47 #define OV5647_REG_CHIPID_L 0x300b
48 #define OV5640_REG_PAD_OUT 0x300d
49 #define OV5647_REG_EXP_HI 0x3500
50 #define OV5647_REG_EXP_MID 0x3501
51 #define OV5647_REG_EXP_LO 0x3502
52 #define OV5647_REG_AEC_AGC 0x3503
[all …]
H A Dov8856.c26 #define OV8856_REG_CHIP_ID 0x300a
27 #define OV8856_CHIP_ID 0x00885a
29 #define OV8856_REG_MODE_SELECT 0x0100
30 #define OV8856_MODE_STANDBY 0x00
31 #define OV8856_MODE_STREAMING 0x01
34 #define OV8856_2A_MODULE 0x01
35 #define OV8856_1B_MODULE 0x02
37 /* the OTP read-out buffer is at 0x7000 and 0xf is the offset
40 #define OV8856_MODULE_REVISION 0x700f
41 #define OV8856_OTP_MODE_CTRL 0x3d84
[all …]
H A Dov5645.c35 #define OV5645_SYSTEM_CTRL0 0x3008
36 #define OV5645_SYSTEM_CTRL0_START 0x02
37 #define OV5645_SYSTEM_CTRL0_STOP 0x42
38 #define OV5645_CHIP_ID_HIGH 0x300a
39 #define OV5645_CHIP_ID_HIGH_BYTE 0x56
40 #define OV5645_CHIP_ID_LOW 0x300b
41 #define OV5645_CHIP_ID_LOW_BYTE 0x45
42 #define OV5645_IO_MIPI_CTRL00 0x300e
43 #define OV5645_PAD_OUTPUT00 0x3019
44 #define OV5645_AWB_MANUAL_CONTROL 0x3406
[all …]
H A Dov13858.c17 #define OV13858_REG_MODE_SELECT 0x0100
18 #define OV13858_MODE_STANDBY 0x00
19 #define OV13858_MODE_STREAMING 0x01
21 #define OV13858_REG_SOFTWARE_RST 0x0103
22 #define OV13858_SOFTWARE_RST 0x01
25 #define OV13858_REG_PLL1_CTRL_0 0x0300
26 #define OV13858_REG_PLL1_CTRL_1 0x0301
27 #define OV13858_REG_PLL1_CTRL_2 0x0302
28 #define OV13858_REG_PLL1_CTRL_3 0x0303
29 #define OV13858_REG_PLL1_CTRL_4 0x0304
[all …]
H A Dov7251.c26 #define OV7251_SC_MODE_SELECT 0x0100
27 #define OV7251_SC_MODE_SELECT_SW_STANDBY 0x0
28 #define OV7251_SC_MODE_SELECT_STREAMING 0x1
30 #define OV7251_CHIP_ID_HIGH 0x300a
31 #define OV7251_CHIP_ID_HIGH_BYTE 0x77
32 #define OV7251_CHIP_ID_LOW 0x300b
33 #define OV7251_CHIP_ID_LOW_BYTE 0x50
34 #define OV7251_SC_GP_IO_IN1 0x3029
35 #define OV7251_AEC_EXPO_0 0x3500
36 #define OV7251_AEC_EXPO_1 0x3501
[all …]
/openbmc/phosphor-logging/extensions/openpower-pels/registry/
H A Dmessage_registry.json9 "ReasonCode": "0x1001",
31 "ReasonCode": "0x1002",
52 "ReasonCode": "0x1003",
68 "ReasonCode": "0x1004",
85 "ReasonCode": "0x1005",
102 "ReasonCode": "0x1006",
117 "ReasonCode": "0x1007",
146 "ReasonCode": "0x1008",
175 "ReasonCode": "0x1009",
204 "ReasonCode": "0x100A",
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8569si-post.dtsi39 interrupts = <19 2 0 0>;
40 sleep = <&pmc 0x08000000>;
43 /* controller at 0xa000 */
49 bus-range = <0 255>;
51 interrupts = <26 2 0 0>;
52 sleep = <&pmc 0x20000000>;
54 pcie@0 {
55 reg = <0 0 0 0 0>;
60 interrupts = <26 2 0 0>;
61 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
[all …]
H A Doss_3_0_1_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
[all …]
H A Doss_2_0_d.h27 #define mmIH_VMID_0_LUT 0xf50
28 #define mmIH_VMID_1_LUT 0xf51
29 #define mmIH_VMID_2_LUT 0xf52
30 #define mmIH_VMID_3_LUT 0xf53
31 #define mmIH_VMID_4_LUT 0xf54
32 #define mmIH_VMID_5_LUT 0xf55
33 #define mmIH_VMID_6_LUT 0xf56
34 #define mmIH_VMID_7_LUT 0xf57
35 #define mmIH_VMID_8_LUT 0xf58
36 #define mmIH_VMID_9_LUT 0xf59
[all …]
H A Doss_3_0_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
[all …]
/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h9 #define SEC_OFFSET 0x4000
15 /* offset: 0x0 */
16 #define DP_PHY_GLB_BIAS_GEN_00 0x0
18 #define DP_PHY_GLB_DPAUX_TX 0x8
20 #define MTK_DP_0034 0x34
36 #define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0)
37 #define DP_PHY_LANE_TX_0 0x104
40 #define DP_PHY_LANE_TX_1 0x204
43 #define DP_PHY_LANE_TX_2 0x304
46 #define DP_PHY_LANE_TX_3 0x404
[all …]

1234