| /openbmc/linux/Documentation/scsi/ |
| H A D | g_NCR5380.rst | 22 for the correct IRQ line automatically. If the irq parameter is 0 or 255
42 0 NCR5380,
65 modprobe g_NCR5380 irq=5 base=0x350 card=1
69 modprobe g_NCR5380 ncr_irq=5 ncr_addr=0x350 ncr_53c400=1
73 modprobe g_NCR5380 base=0x350 card=0
77 modprobe g_NCR5380 ncr_addr=0x350 ncr_5380=1
81 modprobe g_NCR5380 irq=255 base=0xc8000 card=1
85 modprobe g_NCR5380 ncr_irq=255 ncr_addr=0xc8000 ncr_53c400=1
87 E.g. two cards, DTC3181 (in non-PnP mode) at 0x240 with no IRQ
88 and HP C2502 at 0x300 with IRQ 7::
[all …]
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| /openbmc/linux/drivers/media/radio/ |
| H A D | radio-aztech.c | 35 MODULE_VERSION("1.0.0");
37 /* acceptable ports: 0x350 (JP3 shorted), 0x358 (JP3 open) */
44 static int io[AZTECH_MAX] = { [0] = CONFIG_RADIO_AZTECH_PORT,
46 static int radio_nr[AZTECH_MAX] = { [0 ... (AZTECH_MAX - 1)] = -1 };
49 MODULE_PARM_DESC(io, "I/O addresses of the Aztech card (0x350 or 0x358)");
59 #define AZTECH_BIT_NOT_TUNED (1 << 0)
65 /* bits 0 and 2 are volume control, bits 3..5 are not connected */
94 return 0; in aztech_s_frequency()
106 return (inb(isa->io) & AZTECH_BIT_NOT_TUNED) ? 0 : 0xffff; in aztech_g_signal()
114 vol = 0; in aztech_s_mute_volume()
[all …]
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| H A D | Kconfig | 254 hex "Aztech/Packard Bell I/O port (0x350 or 0x358)"
258 Enter either 0x350 or 0x358 here. The card default is 0x350, if you
260 jumper sets the card to 0x358.
291 hex "Fixed I/O port (0x20c, 0x30c, 0x24c, 0x34c, 0x248 or 0x28c)"
295 Enter either 0x20c, 0x30c, 0x24c, 0x34c, 0x248 or 0x28c here. The
296 card default is 0x34c, if you haven't changed the jumper setting
300 port is 0x20c, 0x248 or 0x28c.
311 following ports will be probed: 0x20c, 0x30c, 0x24c, 0x34c, 0x248 and
312 0x28c.
349 You must also pass the module a suitable io parameter, 0x248 has
[all …]
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| H A D | radio-trust.c | 34 /* acceptable ports: 0x350 (JP3 shorted), 0x358 (JP3 open) */
42 static int io[TRUST_MAX] = { [0] = CONFIG_RADIO_TRUST_PORT,
44 static int radio_nr[TRUST_MAX] = { [0 ... (TRUST_MAX - 1)] = -1 };
47 MODULE_PARM_DESC(io, "I/O addresses of the Trust FM Radio card (0x350 or 0x358)");
64 #define TDA7318_ADDR 0x88
65 #define TSA6060T_ADDR 0xc4
67 #define TR_DELAY do { inb(tr->isa.io); inb(tr->isa.io); inb(tr->isa.io); } while (0)
69 #define TR_CLR_SCL outb(tr->ioval &= 0xfd, tr->isa.io)
71 #define TR_CLR_SDA outb(tr->ioval &= 0xfe, tr->isa.io)
90 for (mask = 0x80; mask; mask >>= 1) { in write_i2c()
[all …]
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| /openbmc/linux/tools/testing/selftests/rseq/ |
| H A D | rseq-mips.h | 12 * 0350000d break 0x350
15 * 00100350 break 0x350
18 * 0000d407 break 0x350
26 # define RSEQ_SIG 0x03500010
28 # define RSEQ_SIG 0x00100350
32 # define RSEQ_SIG 0xd4070000
34 # define RSEQ_SIG 0x0000d407
37 # define RSEQ_SIG 0x0350000d
59 } while (0)
75 # define U32_U64_PAD(x) "0x0, " x
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/thermal/ |
| H A D | ti,j72xx-thermal.yaml | 76 reg = <0x42040000 0x350>,
77 <0x42050000 0x350>,
78 <0x43000300 0x10>;
86 thermal-sensors = <&wkup_vtm0 0>;
|
| /openbmc/linux/drivers/video/ |
| H A D | screen_info_generic.c | 12 memset(r, 0, sizeof(*r)); in resource_init_named()
37 case 0x0d: /* 320x200-4 */ in __screen_info_has_ega_gfx()
38 case 0x0e: /* 640x200-4 */ in __screen_info_has_ega_gfx()
39 case 0x0f: /* 640x350-1 */ in __screen_info_has_ega_gfx()
40 case 0x10: /* 640x350-4 */ in __screen_info_has_ega_gfx()
50 case 0x10: /* 640x480-1 */ in __screen_info_has_vga_gfx()
51 case 0x12: /* 640x480-4 */ in __screen_info_has_vga_gfx()
52 case 0x13: /* 320-200-8 */ in __screen_info_has_vga_gfx()
53 case 0x6a: /* 800x600-4 (VESA) */ in __screen_info_has_vga_gfx()
82 if (num > 0) in screen_info_resources()
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-s32v234/ |
| H A D | mc_rgm_regs.h | 10 #define MC_RGM_FES (MC_RGM_BASE_ADDR + 0x300)
11 #define MC_RGM_FERD (MC_RGM_BASE_ADDR + 0x310)
12 #define MC_RGM_FBRE (MC_RGM_BASE_ADDR + 0x330)
13 #define MC_RGM_FESS (MC_RGM_BASE_ADDR + 0x340)
14 #define MC_RGM_DDR_HE (MC_RGM_BASE_ADDR + 0x350)
15 #define MC_RGM_DDR_HS (MC_RGM_BASE_ADDR + 0x354)
16 #define MC_RGM_FRHE (MC_RGM_BASE_ADDR + 0x358)
17 #define MC_RGM_FREC (MC_RGM_BASE_ADDR + 0x600)
18 #define MC_RGM_FRET (MC_RGM_BASE_ADDR + 0x607)
19 #define MC_RGM_DRET (MC_RGM_BASE_ADDR + 0x60B)
[all …]
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| /openbmc/linux/drivers/media/usb/gspca/ |
| H A D | stk1135.h | 8 #define STK1135_REG_GCTRL 0x000 /* GPIO control */
9 #define STK1135_REG_ICTRL 0x004 /* Interrupt control */
10 #define STK1135_REG_IDATA 0x008 /* Interrupt data */
11 #define STK1135_REG_RMCTL 0x00c /* Remote wakeup control */
12 #define STK1135_REG_POSVA 0x010 /* Power-on strapping data */
14 #define STK1135_REG_SENSO 0x018 /* Sensor select options */
15 #define STK1135_REG_PLLFD 0x01c /* PLL frequency divider */
17 #define STK1135_REG_SCTRL 0x100 /* Sensor control register */
18 #define STK1135_REG_DCTRL 0x104 /* Decimation control register */
19 #define STK1135_REG_CISPO 0x110 /* Capture image starting position */
[all …]
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| /openbmc/linux/drivers/char/mwave/ |
| H A D | README | 8 0x0001 mwavedd api tracing
9 0x0002 smapi api tracing
10 0x0004 3780i tracing
11 0x0008 tp3780i tracing
22 mwave_3780i_io=0x130/0x350/0x0070/0xDB0
32 mwave_uart_io=0x3f8/0x2f8/0x3E8/0x2E8
39 insmod mwave mwave_3780i_irq=10 mwave_3780i_io=0x0130 mwave_uart_irq=3 mwave_uart_io=0x2f8
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| /openbmc/u-boot/arch/x86/include/asm/ |
| H A D | lapic.h | 11 #define LAPIC_DEFAULT_BASE 0xfee00000
13 #define LAPIC_ID 0x020
14 #define LAPIC_LVR 0x030
16 #define LAPIC_TASKPRI 0x080
17 #define LAPIC_TPRI_MASK 0xff
19 #define LAPIC_RRR 0x0c0
21 #define LAPIC_SPIV 0x0f0
22 #define LAPIC_SPIV_ENABLE 0x100
24 #define LAPIC_ICR 0x300
25 #define LAPIC_DEST_SELF 0x40000
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
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| H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
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| /openbmc/linux/include/linux/bcma/ |
| H A D | bcma_driver_gmac_cmn.h | 7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
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| /openbmc/u-boot/include/configs/ |
| H A D | ti_omap5_common.h | 71 * area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
72 * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
81 * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
83 #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000
90 #if (CONFIG_TI_SECURE_EMIF_REGION_START == 0)
96 * downloaded into internal RAM at address 0x40300000.
98 #define CONFIG_SPL_TEXT_BASE 0x40300000
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
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| H A D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
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| H A D | imx50-pinfunc.h | 13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
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| /openbmc/linux/drivers/media/usb/stk1160/ |
| H A D | stk1160-reg.h | 14 #define STK1160_GCTRL 0x000
17 #define STK1160_RMCTL 0x00c
20 #define STK1160_POSVA 0x010
21 #define STK1160_POSV_L 0x010
22 #define STK1160_POSV_M 0x011
23 #define STK1160_POSV_H 0x012
30 * with bit #7 (0x?? OR 0x80 to activate).
32 #define STK1160_DCTRL 0x100
39 * Bit 0 - Horizontal Decimation Control
40 * 0 Horizontal decimation is disabled.
[all …]
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| /openbmc/linux/drivers/net/ethernet/mediatek/ |
| H A D | mtk_ppe_regs.h | 7 #define MTK_PPE_GLO_CFG 0x200
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
23 #define MTK_PPE_FLOW_CFG 0x204
42 #define MTK_PPE_IP_PROTO_CHK 0x208
43 #define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
46 #define MTK_PPE_TB_CFG 0x21c
47 #define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
63 #define MTK_PPE_BIND_LMT1 0x230
66 #define MTK_PPE_KEEPALIVE 0x234
86 #define MTK_PPE_TB_BASE 0x220
[all …]
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | am4.h | 8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
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| /openbmc/linux/arch/sh/include/mach-sdk7786/mach/ |
| H A D | fpga.h | 9 #define SRSTR 0x000
10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
12 #define INTASR 0x010
13 #define INTAMR 0x020
14 #define MODSWR 0x030
15 #define INTTESTR 0x040
16 #define SYSSR 0x050
17 #define NRGPR 0x060
19 #define NMISR 0x070
20 #define NMISR_MAN_NMI BIT(0)
[all …]
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| /openbmc/linux/drivers/media/platform/via/ |
| H A D | via-camera.h | 5 #define VCR_INTCTRL 0x300 /* Capture interrupt control */
6 #define VCR_IC_EAV 0x0001 /* End of active video status */
7 #define VCR_IC_EVBI 0x0002 /* End of VBI status */
8 #define VCR_IC_FBOTFLD 0x0004 /* "flipping" Bottom field is active */
9 #define VCR_IC_ACTBUF 0x0018 /* Active video buffer */
10 #define VCR_IC_VSYNC 0x0020 /* 0 = VB, 1 = active video */
11 #define VCR_IC_BOTFLD 0x0040 /* Bottom field is active */
12 #define VCR_IC_FFULL 0x0080 /* FIFO full */
13 #define VCR_IC_INTEN 0x0100 /* End of active video int. enable */
14 #define VCR_IC_VBIINT 0x0200 /* End of VBI int enable */
[all …]
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| /openbmc/u-boot/arch/arm/mach-rmobile/include/mach/ |
| H A D | sh73a0.h | 5 #define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
6 #define MERAM_BASE (0xE5580000)
9 #define GIC_BASE (0xF0000100)
13 #define LIFEC_SEC_SRC (0xE6110008)
16 #define RWDT_BASE (0xE6020000)
19 #define HPB_BASE (0xE6001010)
22 #define HPBSCR_BASE (0xE6001600)
25 #define SBSC1_BASE (0xFE400000)
26 #define SDMRA1A (SBSC1_BASE + 0x100000)
27 #define SDMRA2A (SBSC1_BASE + 0x1C0000)
[all …]
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| /openbmc/linux/drivers/crypto/qce/ |
| H A D | regs-v5.h | 11 #define REG_VERSION 0x000
12 #define REG_STATUS 0x100
13 #define REG_STATUS2 0x104
14 #define REG_ENGINES_AVAIL 0x108
15 #define REG_FIFO_SIZES 0x10c
16 #define REG_SEG_SIZE 0x110
17 #define REG_GOPROC 0x120
18 #define REG_ENCR_SEG_CFG 0x200
19 #define REG_ENCR_SEG_SIZE 0x204
20 #define REG_ENCR_SEG_START 0x208
[all …]
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