/openbmc/u-boot/doc/imx/misc/ |
H A D | sdp.txt | 56 0x1b67:0x4fff, mx6_usb_sdp_spl.conf 61 hid,uboot_header,1024,0x910000,0x10000000,1G,0x00900000,0x40000 77 hid,1024,0x10000000,1G,0x00907000,0x31000 78 full.itb:load 0x12100000 79 boot.scr:load 0x12000000,jump 0x12000000 85 0x15a2:0x0061, mx6_usb_rom.conf, 0x1b67:0x4fff, mx6_usb_sdp_spl.conf 93 hid,1024,0x910000,0x10000000,1G,0x00900000,0x40000 99 hid,uboot_header,1024,0x10000000,1G,0x00907000,0x31000
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/openbmc/linux/Documentation/devicetree/bindings/reset/ |
H A D | qcom,aoss-reset.yaml | 50 reg = <0xc2a0000 0x31000>;
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/openbmc/linux/arch/arm/boot/dts/unisoc/ |
H A D | rda8810pl.dtsi | 19 #size-cells = <0>; 21 cpu@0 { 24 reg = <0x0>; 30 reg = <0x100000 0x10000>; 40 ranges = <0x0 0x10000000 0xfffffff>; 44 reg = <0x1a08000 0x1000>; 55 ranges = <0x0 0x20800000 0x100000>; 57 intc: interrupt-controller@0 { 59 reg = <0x0 0x1000>; 69 ranges = <0x0 0x20900000 0x100000>; [all …]
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/openbmc/u-boot/arch/arm/mach-orion5x/ |
H A D | lowlevel_init.S | 17 #define SDRAM_CONFIG 0x3148400 18 #define SDRAM_MODE 0x62 19 #define SDRAM_CONTROL 0x4041000 20 #define SDRAM_TIME_CTRL_LOW 0x11602220 21 #define SDRAM_TIME_CTRL_HI 0x40c 22 #define SDRAM_OPEN_PAGE_EN 0x0 24 #define SDRAM_BANK0_SIZE 0x3ff0001 25 #define SDRAM_ADDR_CTRL 0x10 27 #define SDRAM_OP_NOP 0x05 28 #define SDRAM_OP_SETMODE 0x03 [all …]
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/openbmc/linux/arch/arm/boot/dts/broadcom/ |
H A D | bcm-hr2.dtsi | 45 #size-cells = <0>; 47 cpu0: cpu@0 { 51 reg = <0x0>; 64 ranges = <0x00000000 0x19000000 0x00023000>; 68 a9pll: arm_clk@0 { 69 #clock-cells = <0>; 72 reg = <0x0 0x1000>; 77 reg = <0x20200 0x100>; 84 reg = <0x20600 0x20>; 92 reg = <0x20620 0x20>; [all …]
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H A D | bcm-nsp.dtsi | 54 #size-cells = <0>; 56 cpu0: cpu@0 { 60 reg = <0x0>; 68 secondary-boot-reg = <0xffff0fec>; 69 reg = <0x1>; 82 ranges = <0x00000000 0x19000000 0x00023000>; 86 a9pll: arm_clk@0 { 87 #clock-cells = <0>; 90 reg = <0x00000 0x1000>; 95 reg = <0x20200 0x100>; [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap2430.dtsi | 18 ranges = <0 0x49000000 0x31000>; 22 reg = <0x6000 0x1000>; 26 #size-cells = <0>; 35 reg = <0x2000 0x1000>; 39 ranges = <0 0x2000 0x1000>; 44 reg = <0x30 0x0154>; 46 #size-cells = <0>; 49 pinctrl-single,function-mask = <0x3f>; 55 reg = <0x270 0x240>; 58 ranges = <0 0x270 0x240>; [all …]
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H A D | am33xx-l4.dtsi | 1 &l4_wkup { /* 0x44c00000 */ 4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; 6 reg = <0x44c00000 0x800>, 7 <0x44c00800 0x800>, 8 <0x44c01000 0x400>, 9 <0x44c01400 0x400>; 13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 17 segment@0 { /* 0x44c00000 */ [all …]
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H A D | am437x-l4.dtsi | 1 &l4_wkup { /* 0x44c00000 */ 4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; 6 reg = <0x44c00000 0x800>, 7 <0x44c00800 0x800>, 8 <0x44c01000 0x400>, 9 <0x44c01400 0x400>; 13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 17 segment@0 { /* 0x44c00000 */ [all …]
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/openbmc/linux/drivers/rapidio/switches/ |
H A D | idt_gen3.c | 18 #define RIO_EM_PW_STAT 0x40020 19 #define RIO_PW_CTL 0x40204 20 #define RIO_PW_CTL_PW_TMR 0xffffff00 21 #define RIO_PW_ROUTE 0x40208 23 #define RIO_EM_DEV_INT_EN 0x40030 25 #define RIO_PLM_SPx_IMP_SPEC_CTL(x) (0x10100 + (x)*0x100) 26 #define RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST 0x02000000 28 #define RIO_PLM_SPx_PW_EN(x) (0x10118 + (x)*0x100) 29 #define RIO_PLM_SPx_PW_EN_OK2U 0x40000000 30 #define RIO_PLM_SPx_PW_EN_LINIT 0x10000000 [all …]
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/openbmc/u-boot/arch/arm/mach-sunxi/ |
H A D | dram_sun8i_a23.c | 35 .para1 = 0, /* not used (only used when tpr13 bit 31 is set */ 36 .para2 = 0, /* not used (only used when tpr13 bit 31 is set */ 40 .mr3 = 0, 42 .tpr0 = 0x2ab83def, 43 .tpr1 = 0x18082356, 44 .tpr2 = 0x00034156, 45 .tpr3 = 0x448c5533, 46 .tpr4 = 0x08010d00, 47 .tpr5 = 0x0340b20f, 48 .tpr6 = 0x20d118cc, [all …]
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/openbmc/qemu/hw/arm/ |
H A D | stm32f405_soc.c | 33 #define RCC_ADDR 0x40023800 34 #define SYSCFG_ADD 0x40013800 35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, 36 0x40004C00, 0x40005000, 0x40011400, 37 0x40007800, 0x40007C00 }; 39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, 40 0x40000800, 0x40000C00 }; 41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200, 42 0x40012300, 0x40012400, 0x40012500 }; 43 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, [all …]
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/openbmc/linux/arch/powerpc/boot/dts/fsl/ |
H A D | t1023si-post.dtsi | 39 alloc-ranges = <0 0 0x10000 0>; 44 alloc-ranges = <0 0 0x10000 0>; 49 alloc-ranges = <0 0 0x10000 0>; 56 interrupts = <25 2 0 0>; 64 bus-range = <0x0 0xff>; 65 interrupts = <20 2 0 0>; 67 pcie@0 { 68 reg = <0 0 0 0 0>; 73 interrupts = <20 2 0 0>; 74 interrupt-map-mask = <0xf800 0 0 7>; [all …]
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H A D | b4si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x200000 */ 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 66 pcie@0 { 71 reg = <0 0 0 0 0>; 72 interrupts = <20 2 0 0>; [all …]
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H A D | t2081si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x240000 */ 59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie"; 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 66 pcie@0 { 67 reg = <0 0 0 0 0>; [all …]
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H A D | t1040si-post.dtsi | 39 alloc-ranges = <0 0 0x10000 0>; 44 alloc-ranges = <0 0 0x10000 0>; 49 alloc-ranges = <0 0 0x10000 0>; 56 interrupts = <25 2 0 0>; 64 bus-range = <0x0 0xff>; 65 interrupts = <20 2 0 0>; 67 pcie@0 { 68 reg = <0 0 0 0 0>; 73 interrupts = <20 2 0 0>; 74 interrupt-map-mask = <0xf800 0 0 7>; [all …]
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H A D | t4240si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x240000 */ 59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 65 pcie@0 { 70 reg = <0 0 0 0 0>; [all …]
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/openbmc/linux/drivers/net/wireless/intersil/orinoco/ |
H A D | hw.c | 34 {110, 1, 3, 15}, /* Entry 0 is the default */ 35 {10, 0, 1, 1}, 37 {20, 0, 2, 2}, 39 {55, 0, 4, 4}, 41 {110, 0, 5, 8}, 52 if (nic_id->id < 0x8000) in determine_firmware_type() 54 else if (nic_id->id == 0x8000 && nic_id->major == 0) in determine_firmware_type() 96 *hw_ver = (((nic_id.id & 0xff) << 24) | in determine_fw_capabilities() 97 ((nic_id.variant & 0xff) << 16) | in determine_fw_capabilities() 98 ((nic_id.major & 0xff) << 8) | in determine_fw_capabilities() [all …]
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/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | sc7180.dtsi | 63 #clock-cells = <0>; 69 #clock-cells = <0>; 75 #size-cells = <0>; 77 cpu0: cpu@0 { 80 reg = <0x0 0x0>; 81 clocks = <&cpufreq_hw 0>; 92 qcom,freq-domain = <&cpufreq_hw 0>; 109 reg = <0x0 0x100>; 110 clocks = <&cpufreq_hw 0>; 121 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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H A D | sm6350.dtsi | 31 #clock-cells = <0>; 39 #clock-cells = <0>; 45 #size-cells = <0>; 47 CPU0: cpu@0 { 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 80 reg = <0x0 0x100>; 81 clocks = <&cpufreq_hw 0>; 86 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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/openbmc/linux/drivers/clk/qcom/ |
H A D | gcc-msm8916.c | 45 .l_reg = 0x21004, 46 .m_reg = 0x21008, 47 .n_reg = 0x2100c, 48 .config_reg = 0x21010, 49 .mode_reg = 0x21000, 50 .status_reg = 0x2101c, 63 .enable_reg = 0x45000, 64 .enable_mask = BIT(0), 76 .l_reg = 0x20004, 77 .m_reg = 0x20008, [all …]
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H A D | gcc-msm8996.c | 49 .offset = 0x00000, 52 .enable_reg = 0x52000, 53 .enable_mask = BIT(0), 79 .offset = 0x00000, 94 .enable_reg = 0x5200c, 95 .enable_mask = BIT(0), 111 .enable_reg = 0x5200c, 126 .offset = 0x77000, 129 .enable_reg = 0x52000, 143 .offset = 0x77000, [all …]
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H A D | gcc-ipq5332.c | 51 .offset = 0x20000, 54 .enable_reg = 0xb000, 55 .enable_mask = BIT(0), 78 .offset = 0x20000, 91 .offset = 0x21000, 94 .enable_reg = 0xb000, 106 .offset = 0x21000, 119 .offset = 0x22000, 122 .enable_reg = 0xb000, 145 .offset = 0x22000, [all …]
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H A D | gcc-msm8939.c | 53 .l_reg = 0x21004, 54 .m_reg = 0x21008, 55 .n_reg = 0x2100c, 56 .config_reg = 0x21010, 57 .mode_reg = 0x21000, 58 .status_reg = 0x2101c, 71 .enable_reg = 0x45000, 72 .enable_mask = BIT(0), 84 .l_reg = 0x20004, 85 .m_reg = 0x20008, [all …]
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/openbmc/u-boot/arch/powerpc/include/asm/ |
H A D | immap_85xx.h | 28 #define CCSRAR_C 0x80000000 /* Commit */ 37 u8 res3[0xbd4]; 44 u8 res35[0x204]; 57 u32 lawbar0; /* Local Access Window 0 Base Addr */ 59 u32 lawar0; /* Local Access Window 0 Attrs */ 117 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */ 118 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */ 177 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */ 178 u8 res2[4048]; /* fill up to 0x1000 */ 191 u32 potar0; /* PCIX Outbound Transaction Addr 0 */ [all …]
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