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/openbmc/linux/drivers/soc/qcom/
H A Dqcom_gsbi.c17 #define GSBI_CTRL_REG 0x0000
21 #define TCSR_ADM_CRCI_BASE 0x70
30 0x000003, 0x00000c, 0x000030, 0x0000c0,
31 0x000300, 0x000c00, 0x003000, 0x00c000,
32 0x030000, 0x0c0000, 0x300000, 0xc00000
35 0x000003, 0x00000c, 0x000030, 0x0000c0,
36 0x000300, 0x000c00, 0x003000, 0x00c000,
37 0x030000, 0x0c0000, 0x300000, 0xc00000
48 0x001800, 0x006000, 0x000030, 0x0000c0,
49 0x000300, 0x000400, 0x000000, 0x000000,
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dcpu_ca53_cfg_masks.h23 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0
24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3
26 #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30
28 #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300
30 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000
33 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0
34 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF
37 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0
38 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF
41 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm8150-pinctrl.yaml72 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
124 reg = <0x03100000 0x300000>,
125 <0x03500000 0x300000>,
126 <0x03900000 0x300000>,
127 <0x03d00000 0x300000>;
130 gpio-ranges = <&tlmm 0 0 176>;
H A Dqcom,sm8250-pinctrl.yaml70 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
116 reg = <0x0f100000 0x300000>,
117 <0x0f500000 0x300000>,
118 <0x0f900000 0x300000>;
125 gpio-ranges = <&tlmm 0 0 181>; /* GPIOs + ufs_reset */
H A Dqcom,sm7150-tlmm.yaml74 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
122 reg = <0x03500000 0x300000>,
123 <0x03900000 0x300000>,
124 <0x03d00000 0x300000>;
127 gpio-ranges = <&tlmm 0 0 120>;
H A Dqcom,sc7180-pinctrl.yaml71 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
123 reg = <0x03500000 0x300000>,
124 <0x03900000 0x300000>,
125 <0x03d00000 0x300000>;
132 gpio-ranges = <&tlmm 0 0 120>;
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/cfg/
H A Dax210.c19 #define IWL_AX210_NVM_VERSION 0x0a1d
22 #define IWL_AX210_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_AX210_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_AX210_DCCM2_OFFSET 0x880000
25 #define IWL_AX210_DCCM2_LEN 0x8000
26 #define IWL_AX210_SMEM_OFFSET 0x400000
27 #define IWL_AX210_SMEM_LEN 0xD0000
96 .mac_addr_from_csr = 0x380, \
103 .min_umac_error_event_table = 0x400000, \
104 .d3_debug_data_base_addr = 0x401000, \
[all …]
H A Dbz.c19 #define IWL_BZ_NVM_VERSION 0x0a1d
22 #define IWL_BZ_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_BZ_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_BZ_DCCM2_OFFSET 0x880000
25 #define IWL_BZ_DCCM2_LEN 0x8000
26 #define IWL_BZ_SMEM_OFFSET 0x400000
27 #define IWL_BZ_SMEM_LEN 0xD0000
82 .mac_addr_from_csr = 0x30, \
88 .min_umac_error_event_table = 0xD0000, \
89 .d3_debug_data_base_addr = 0x401000, \
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-sec4.0-0.dtsi2 * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
47 interrupts = <88 2 0 0>;
51 compatible = "fsl,sec-v4.0-job-ring";
52 reg = <0x2000 0x1000>;
[all …]
H A Dqoriq-sec5.0-0.dtsi2 * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
47 reg = <0x1000 0x1000>;
48 interrupts = <88 2 0 0>;
52 compatible = "fsl,sec-v5.0-job-ring",
[all …]
H A Dqoriq-sec4.2-0.dtsi2 * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
46 "fsl,sec-v4.0-job-ring";
47 reg = <0x1000 0x1000>;
48 interrupts = <88 2 0 0>;
53 "fsl,sec-v4.0-job-ring";
54 reg = <0x2000 0x1000>;
[all …]
H A Dqoriq-sec5.2-0.dtsi2 * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
48 reg = <0x1000 0x1000>;
49 interrupts = <88 2 0 0>;
54 "fsl,sec-v5.0-job-ring",
[all …]
H A Dqoriq-sec5.3-0.dtsi2 * QorIQ Sec/Crypto 5.3 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
48 reg = <0x1000 0x1000>;
49 interrupts = <88 2 0 0>;
54 "fsl,sec-v5.0-job-ring",
[all …]
/openbmc/linux/arch/mips/boot/dts/ralink/
H A Drt2880.dtsi8 cpu@0 {
14 #address-cells = <0>;
22 reg = <0x300000 0x200000>;
23 ranges = <0x0 0x300000 0x1FFFFF>;
28 sysc@0 {
30 reg = <0x0 0x100>;
35 reg = <0x200 0x100>;
46 reg = <0x300 0x100>;
51 reg = <0xc00 0x100>;
/openbmc/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-apf28.dts15 reg = <0x40000000 0x08000000>;
21 pinctrl-0 = <&duart_pins_a>;
27 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
30 partition@0 {
32 reg = <0x0 0x300000>;
37 reg = <0x300000 0x80000>;
42 reg = <0x380000 0x80000>;
47 reg = <0x400000 0x80000>;
52 reg = <0x480000 0x80000>;
57 reg = <0x500000 0x800000>;
[all …]
/openbmc/u-boot/include/configs/
H A Dsmdkc100.h30 #define CONFIG_SYS_SDRAM_BASE 0x30000000
40 * 1MB = 0x100000, 0x100000 = 1024 * 1024
64 #define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \
65 " onenand write 0x32008000 0x0 0x40000\0"
71 "onenand erase 0x60000 0x300000;" \
72 "onenand write 0x31008000 0x60000 0x300000\0" \
75 "onenand write 0x32000000 0x1260000 0x8C0000\0" \
77 "onenand read 0x30007FC0 0x60000 0x300000;" \
78 "bootm 0x30007FC0\0" \
83 "run bootk\0" \
[all …]
H A Dat91sam9m10g45ek.h38 #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000
46 #define CONFIG_SYS_SDRAM_BASE 0x70000000
47 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
70 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
73 #define CONFIG_SYS_MEMTEST_END 0x23e00000
77 #define CONFIG_ENV_OFFSET 0x140000
78 #define CONFIG_ENV_OFFSET_REDUND 0x100000
79 #define CONFIG_ENV_SIZE 0x20000
82 "nand read 0x70000000 0x200000 0x300000;" \
83 "bootm 0x70000000"
[all …]
H A Dat91sam9x5ek.h34 #define CONFIG_SYS_SDRAM_BASE 0x20000000
35 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
45 #define CONFIG_SYS_NAND_BASE 0x40000000
68 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
71 #define CONFIG_SYS_MEMTEST_END 0x26e00000
75 #define CONFIG_ENV_OFFSET 0x140000
76 #define CONFIG_ENV_OFFSET_REDUND 0x100000
77 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
79 "0x22000000 0x200000 0x600000; " \
80 "nand read 0x21000000 0x180000 0x20000; " \
[all …]
H A Dcorvus.h59 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
90 #define CONFIG_ENV_OFFSET 0x100000
91 #define CONFIG_ENV_OFFSET_REDUND 0x180000
95 "nand read 0x70000000 0x200000 0x300000;" \
96 "bootm 0x70000000"
102 SZ_4M, 0x1000)
105 #define CONFIG_SPL_TEXT_BASE 0x300000
117 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
118 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
138 #define CONFIG_SYS_AT91_PLLA 0x20c73f03
[all …]
H A Dat91sam9n12ek.h36 #define CONFIG_SYS_SDRAM_BASE 0x20000000
37 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
45 (0x00300000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
52 #define CONFIG_SYS_NAND_BASE 0x40000000
60 "console=console=ttyS0,115200\0" \
61 "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
62 "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
63 "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
67 #define CONFIG_KS8851_MLL_BASEADDR 0x30000000 /* use NCS2 */
69 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip05-d02.dts17 memory@0 {
19 reg = <0x0 0x00000000 0x0 0x80000000>;
37 debounce-interval = <0>;
54 ranges = <0 0 0x0 0x90000000 0x08000000>,
55 <1 0 0x0 0x98000000 0x08000000>;
57 nor-flash@0,0 {
61 reg = <0 0x0 0x08000000>;
64 partition@0 {
66 reg = <0x0 0x300000>;
70 reg = <0x300000 0xa00000>;
[all …]
/openbmc/u-boot/doc/
H A DREADME.sha129 a) cp the new Image on a position in RAM (here 0x300000)
30 (for this example we use the Image from Flash, stored at 0xfffa0000 and
31 0x60000 Bytes long)
35 b) Initialize the SHA1 sum in the Image with 0x00
38 for the pcs440ep Flash: 0xfffa0000 + 0x60000 + -0x20
39 = 0xffffffe0
40 for the example in RAM: 0x300000 + 0x60000 + -0x20
41 = 0x35ffe0
45 "mw.b 35ffe0 0 14"
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm958625-meraki-mx6x-common.dtsi55 reg = <0x50>;
62 reg = <0x66 0x6>;
68 nand@0 {
70 reg = <0>;
81 partition@0 {
83 reg = <0x0 0x80000>;
89 reg = <0x80000 0x80000>;
95 reg = <0x100000 0x300000>;
100 reg = <0x400000 0x100000>;
105 reg = <0x500000 0x300000>;
[all …]
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]
/openbmc/qemu/tests/qemu-iotests/tests/
H A Dzoned.out5 start: 0x0, len 0x80000, cap 0x80000, wptr 0x0, zcond:1, [type: 2]
8 start: 0x0, len 0x80000, cap 0x80000, wptr 0x0, zcond:1, [type: 2]
9 start: 0x80000, len 0x80000, cap 0x80000, wptr 0x80000, zcond:1, [type: 2]
10 start: 0x100000, len 0x80000, cap 0x80000, wptr 0x100000, zcond:1, [type: 2]
11 start: 0x180000, len 0x80000, cap 0x80000, wptr 0x180000, zcond:1, [type: 2]
12 start: 0x200000, len 0x80000, cap 0x80000, wptr 0x200000, zcond:1, [type: 2]
13 start: 0x280000, len 0x80000, cap 0x80000, wptr 0x280000, zcond:1, [type: 2]
14 start: 0x300000, len 0x80000, cap 0x80000, wptr 0x300000, zcond:1, [type: 2]
15 start: 0x380000, len 0x80000, cap 0x80000, wptr 0x380000, zcond:1, [type: 2]
16 start: 0x400000, len 0x80000, cap 0x80000, wptr 0x400000, zcond:1, [type: 2]
[all …]

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