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2 CONFIG_SYS_TEXT_BASE=0x2900000024 CONFIG_SYS_OS_BASE=0x2c060000
33 enum: [ 0, 1, 2 ]46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI51 SPI interrupts are in the range [0-987]. PPI interrupts are in the52 range [0-15]. Extended SPI interrupts are in the range [0-1023].53 Extended PPI interrupts are in the range [0-127].56 bits[3:0] trigger type and level flags.68 of 0 if present.83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and99 multipleOf: 0x10000100 exclusiveMinimum: 0[all …]