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/openbmc/linux/arch/arm64/boot/dts/arm/
H A Dfoundation-v8-gicv2.dtsi13 reg = <0x0 0x2c001000 0 0x1000>,
14 <0x0 0x2c002000 0 0x2000>,
15 <0x0 0x2c004000 0 0x2000>,
16 <0x0 0x2c006000 0 0x2000>;
H A Dvexpress-v2f-1xv7-ca53x2.dts20 arm,hbi = <0x247>;
21 arm,vexpress,site = <0xf>;
42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0 0>;
54 reg = <0 1>;
67 reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
75 /* Chipselect 2 is physically at 0x18000000 */
79 reg = <0 0x18000000 0 0x00800000>;
87 #address-cells = <0>;
[all …]
H A Drtsm_ve-aemv8a.dts15 /memreserve/ 0x80000000 0x00010000;
37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0x0 0x0>;
44 cpu-release-addr = <0x0 0x8000fff8>;
50 reg = <0x0 0x1>;
52 cpu-release-addr = <0x0 0x8000fff8>;
58 reg = <0x0 0x2>;
60 cpu-release-addr = <0x0 0x8000fff8>;
66 reg = <0x0 0x3>;
[all …]
/openbmc/linux/arch/arm/boot/dts/xen/
H A Dxenvm-4.2.dts26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
51 reg = <0 0x80000000 0 0x08000000>;
57 #address-cells = <0>;
59 reg = <0 0x2c001000 0 0x1000>,
60 <0 0x2c002000 0 0x100>;
65 interrupts = <1 13 0xf08>,
66 <1 14 0xf08>,
67 <1 11 0xf08>,
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15-tc1.dts16 arm,hbi = <0x237>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
53 reg = <0 0x80000000 0 0x40000000>;
61 /* Chipselect 2 is physically at 0x18000000 */
65 reg = <0 0x18000000 0 0x00800000>;
72 reg = <0 0x2b000000 0 0x1000>;
73 interrupts = <0 85 4>;
[all …]
H A Dvexpress-v2p-ca15_a7.dts16 arm,hbi = <0x249>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0>;
61 reg = <0x100>;
71 reg = <0x101>;
81 reg = <0x102>;
109 reg = <0 0x80000000 0 0x40000000>;
117 /* Chipselect 2 is physically at 0x18000000 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic.yaml67 enum: [ 0, 1, 2 ]
74 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
78 SPI interrupts are in the range [0-987]. PPI interrupts are in the
79 range [0-15].
82 bits[3:0] trigger type and level flags.
150 "^v2m@[0-9a-f]+$":
197 reg = <0xfff11000 0x1000>,
198 <0xfff10100 0x100>;
207 reg = <0x2c001000 0x1000>,
208 <0x2c002000 0x2000>,
[all …]
/openbmc/qemu/hw/arm/
H A Dvexpress.c50 #define VEXPRESS_BOARD_ID 0x8e0
54 /* Number of virtio transports to create (0..8; limited by
98 [VE_NORFLASHALIAS] = 0,
99 /* CS7: 0x10000000 .. 0x10020000 */
100 [VE_SYSREGS] = 0x10000000,
101 [VE_SP810] = 0x10001000,
102 [VE_SERIALPCI] = 0x10002000,
103 [VE_PL041] = 0x10004000,
104 [VE_MMCI] = 0x10005000,
105 [VE_KMI0] = 0x10006000,
[all …]