Lines Matching +full:0 +full:x2c002000
16 arm,hbi = <0x249>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0>;
61 reg = <0x100>;
71 reg = <0x101>;
81 reg = <0x102>;
109 reg = <0 0x80000000 0 0x40000000>;
117 /* Chipselect 2 is physically at 0x18000000 */
121 reg = <0 0x18000000 0 0x00800000>;
128 reg = <0 0x2a490000 0 0x1000>;
129 interrupts = <0 98 4>;
136 reg = <0 0x2b000000 0 0x1000>;
137 interrupts = <0 85 4>;
144 reg = <0 0x2b0a0000 0 0x1000>;
152 #address-cells = <0>;
154 reg = <0 0x2c001000 0 0x1000>,
155 <0 0x2c002000 0 0x2000>,
156 <0 0x2c004000 0 0x2000>,
157 <0 0x2c006000 0 0x2000>;
158 interrupts = <1 9 0xf04>;
165 reg = <0 0x2c090000 0 0x1000>;
166 ranges = <0x0 0x0 0x2c090000 0x10000>;
171 reg = <0x4000 0x1000>;
177 reg = <0x5000 0x1000>;
182 reg = <0x9000 0x5000>;
183 interrupts = <0 105 4>,
184 <0 101 4>,
185 <0 102 4>,
186 <0 103 4>,
187 <0 104 4>;
193 reg = <0 0x7ffd0000 0 0x1000>;
194 interrupts = <0 86 4>,
195 <0 87 4>;
202 reg = <0 0x7ff00000 0 0x1000>;
203 interrupts = <0 92 4>,
204 <0 88 4>,
205 <0 89 4>,
206 <0 90 4>,
207 <0 91 4>;
214 reg = <0 0x7fff0000 0 0x1000>;
215 interrupts = <0 95 4>;
220 interrupts = <1 13 0xf08>,
221 <1 14 0xf08>,
222 <1 11 0xf08>,
223 <1 10 0xf08>;
228 interrupts = <0 68 4>,
229 <0 69 4>;
236 interrupts = <0 128 4>,
237 <0 129 4>,
238 <0 130 4>;
247 #clock-cells = <0>;
257 /* A15 PLL 0 reference clock */
259 arm,vexpress-sysreg,func = <1 0>;
261 #clock-cells = <0>;
270 #clock-cells = <0>;
275 /* A7 PLL 0 reference clock */
279 #clock-cells = <0>;
288 #clock-cells = <0>;
297 #clock-cells = <0>;
306 #clock-cells = <0>;
315 #clock-cells = <0>;
324 #clock-cells = <0>;
333 #clock-cells = <0>;
340 arm,vexpress-sysreg,func = <2 0>;
362 arm,vexpress-sysreg,func = <3 0>;
376 arm,vexpress-sysreg,func = <4 0>;
383 arm,vexpress-sysreg,func = <12 0>;
397 arm,vexpress-sysreg,func = <13 0>, <13 1>;
411 reg = <0 0x20010000 0 0x1000>;
426 reg = <0 0x20030000 0 0x1000>;
447 #size-cells = <0>;
449 port@0 {
450 reg = <0>;
475 reg = <0 0x20040000 0 0x1000>;
490 #size-cells = <0>;
492 port@0 {
493 reg = <0>;
533 reg = <0 0x2201c000 0 0x1000>;
549 reg = <0 0x2201d000 0 0x1000>;
565 reg = <0 0x2203c000 0 0x1000>;
581 reg = <0 0x2203d000 0 0x1000>;
597 reg = <0 0x2203e000 0 0x1000>;
612 ranges = <0x8000000 0 0x8000000 0x18000000>;
619 ranges = <0 0 0x40000000 0x3fef0000>;
621 interrupt-map-mask = <0 3>;
622 interrupt-map = <0 0 &gic 0 36 4>,
623 <0 1 &gic 0 37 4>,
624 <0 2 &gic 0 38 4>,
625 <0 3 &gic 0 39 4>;