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/openbmc/u-boot/drivers/clk/sunxi/
H A Dclk_r40.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_SPI2] = GATE(0x060, BIT(22)),
23 [CLK_BUS_SPI3] = GATE(0x060, BIT(23)),
24 [CLK_BUS_OTG] = GATE(0x060, BIT(25)),
25 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
[all …]
H A Dclk_h3.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
25 [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)),
[all …]
H A Dclk_a31.c16 [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
20 [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
21 [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
23 [CLK_AHB1_SPI2] = GATE(0x060, BIT(22)),
24 [CLK_AHB1_SPI3] = GATE(0x060, BIT(23)),
25 [CLK_AHB1_OTG] = GATE(0x060, BIT(24)),
[all …]
H A Dclk_a64.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
25 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
[all …]
H A Dclk_a83t.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
25 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
[all …]
H A Dclk_a23.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
20 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
21 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
22 [CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
23 [CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
25 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
26 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[all …]
H A Dclk_v3s.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
20 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
22 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
23 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
24 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
26 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
28 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
[all …]
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun8i-h3.c29 "osc24M", 0x000,
32 0, 2, /* M */
50 #define SUN8I_H3_PLL_AUDIO_REG 0x008
53 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
54 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
58 "osc24M", 0x008,
60 0, 5, /* M */
62 0x284, BIT(31),
68 "osc24M", 0x0010,
72 0, 4, /* M */
[all …]
H A Dccu-sun8i-v3s.c31 "osc24M", 0x000,
34 0, 2, /* M */
38 0);
52 #define SUN8I_V3S_PLL_AUDIO_REG 0x008
55 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
56 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
60 "osc24M", 0x008,
62 0, 5, /* M */
64 0x284, BIT(31),
70 "osc24M", 0x0010,
[all …]
H A Dccu-sun50i-a64.c31 .m = _SUNXI_CCU_DIV(0, 2),
34 .reg = 0x000,
54 #define SUN50I_A64_PLL_AUDIO_REG 0x008
57 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
58 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
62 "osc24M", 0x008,
64 0, 5, /* M */
66 0x284, BIT(31),
72 "osc24M", 0x010,
76 0, 4, /* M */
[all …]
H A Dccu-sun6i-a31.c33 "osc24M", 0x000,
36 0, 2, /* M */
39 0);
53 #define SUN6I_A31_PLL_AUDIO_REG 0x008
56 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
57 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
61 "osc24M", 0x008,
63 0, 5, /* M */
65 0x284, BIT(31),
71 "osc24M", 0x010,
[all …]
H A Dccu-sun8i-a83t.c24 #define CCU_SUN8I_A83T_LOCK_REG 0x20c
33 #define SUN8I_A83T_PLL_C0CPUX_REG 0x000
34 #define SUN8I_A83T_PLL_C1CPUX_REG 0x004
38 .lock = BIT(0),
39 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
53 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
68 * which is d1 = 0, d2 = 1.
70 #define SUN8I_A83T_PLL_AUDIO_REG 0x008
74 { .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },
75 { .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 },
[all …]
H A Dccu-sun8i-r40.c33 .m = _SUNXI_CCU_DIV(0, 2),
36 .reg = 0x000,
56 #define SUN8I_R40_PLL_AUDIO_REG 0x008
59 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
60 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
64 "osc24M", 0x008,
66 0, 5, /* M */
68 0x284, BIT(31),
74 "osc24M", 0x0010,
78 0, 4, /* M */
[all …]
H A Dccu-sun8i-a33.c32 .m = _SUNXI_CCU_DIV(0, 2),
36 .reg = 0x000,
39 0),
55 #define SUN8I_A33_PLL_AUDIO_REG 0x008
58 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
59 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
63 "osc24M", 0x008,
65 0, 5, /* M */
67 0x284, BIT(31),
73 "osc24M", 0x010,
[all …]
H A Dccu-sun8i-a23.c34 .m = _SUNXI_CCU_DIV(0, 2),
38 .reg = 0x000,
41 0),
57 #define SUN8I_A23_PLL_AUDIO_REG 0x008
60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
65 "osc24M", 0x008,
67 0, 5, /* M */
69 0x284, BIT(31),
75 "osc24M", 0x010,
[all …]
H A Dccu-suniv-f1c100s.c33 .m = _SUNXI_CCU_DIV(0, 2),
38 .reg = 0x000,
53 #define SUNIV_PLL_AUDIO_REG 0x008
56 "osc24M", 0x008,
58 0, 5, /* M */
64 "osc24M", 0x010,
66 0, 4, /* M */
69 270000000, /* frac rate 0 */
76 "osc24M", 0x018,
78 0, 4, /* M */
[all …]
/openbmc/linux/drivers/pci/controller/
H A Dpcie-iproc-msi.c20 #define IPROC_MSI_EQ_EN_SHIFT 0
23 #define IPROC_MSI_EQ_MASK 0x3f
38 IPROC_MSI_EQ_PAGE = 0,
113 { 0x200, 0x2c0, 0x204, 0x2c4, 0x210, 0x250, 0x254, 0x208 },
114 { 0x200, 0x2c0, 0x204, 0x2c4, 0x214, 0x258, 0x25c, 0x208 },
115 { 0x200, 0x2c0, 0x204, 0x2c4, 0x218, 0x260, 0x264, 0x208 },
116 { 0x200, 0x2c0, 0x204, 0x2c4, 0x21c, 0x268, 0x26c, 0x208 },
117 { 0x200, 0x2c0, 0x204, 0x2c4, 0x220, 0x270, 0x274, 0x208 },
118 { 0x200, 0x2c0, 0x204, 0x2c4, 0x224, 0x278, 0x27c, 0x208 },
122 { 0xc00, 0xc04, 0xc08, 0xc0c, 0xc40, 0xc50, 0xc60 },
[all …]
/openbmc/linux/arch/sh/boards/
H A Dboard-sh2007.c21 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
22 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
34 [0] = {
36 .end = SMC0_BASE + 0xff,
40 .start = evt2irq(0x240),
41 .end = evt2irq(0x240),
47 [0] = {
49 .end = SMC1_BASE + 0xff,
53 .start = evt2irq(0x280),
54 .end = evt2irq(0x280),
[all …]
/openbmc/linux/arch/sh/boards/mach-sdk7786/
H A Dsetup.c28 .start = 0x07fff8b0,
29 .end = 0x07fff8b0 + sizeof(u16) - 1,
47 [0] = {
49 .start = 0x07ffff00,
50 .end = 0x07ffff00 + SZ_256 - 1,
55 .start = evt2irq(0x2c0),
56 .end = evt2irq(0x2c0),
79 .start = 0x07fff9e0,
80 .end = 0x07fff9e0 + SZ_32 - 1,
86 .id = 0,
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Deeprom.h12 MT_EE_CHIP_ID = 0x000,
13 MT_EE_VERSION = 0x002,
14 MT_EE_MAC_ADDR = 0x004,
15 MT_EE_MAC_ADDR2 = 0x00a,
16 MT_EE_WIFI_CONF = 0x190,
17 MT_EE_MAC_ADDR3 = 0x2c0,
18 MT_EE_RATE_DELTA_2G = 0x1400,
19 MT_EE_RATE_DELTA_5G = 0x147d,
20 MT_EE_RATE_DELTA_6G = 0x154a,
21 MT_EE_TX0_POWER_2G = 0x1300,
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dsama5_matrix.h13 u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */
14 u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */
15 u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
16 u32 res1[20]; /* 0x100 ~ 0x14c */
17 u32 meier; /* 0x150: Master Error Interrupt Enable Register */
18 u32 meidr; /* 0x154: Master Error Interrupt Disable Register */
19 u32 meimr; /* 0x158: Master Error Interrupt Mask Register */
20 u32 mesr; /* 0x15c: Master Error Status Register */
21 u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */
22 u32 res2[17]; /* 0x1A0 ~ 0x1E0 */
[all …]
/openbmc/linux/arch/sh/include/mach-landisk/mach/
H A Diodata_landisk.h16 #define PA_USB 0xa4000000 /* USB Controller M66590 */
18 #define PA_ATARST 0xb0000000 /* ATA/FATA Access Control Register */
19 #define PA_LED 0xb0000001 /* LED Control Register */
20 #define PA_STATUS 0xb0000002 /* Switch Status Register */
21 #define PA_SHUTDOWN 0xb0000003 /* Shutdown Control Register */
22 #define PA_PCIPME 0xb0000004 /* PCI PME Status Register */
23 #define PA_IMASK 0xb0000005 /* Interrupt Mask Register */
25 #define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
27 #define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */
28 #define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Damlogic,meson-pinctrl-g12a-periphs.yaml24 "^bank@[0-9a-z]+$":
57 reg = <0x40 0x4c>,
58 <0xe8 0x18>,
59 <0x120 0x18>,
60 <0x2c0 0x40>,
61 <0x340 0x1c>;
65 gpio-ranges = <&periphs_pinctrl 0 0 86>;
/openbmc/linux/Documentation/translations/zh_CN/dev-tools/
H A Dkasan.rst55 通用KASAN需要GCC 8.3.0版本或更高版本，或者内核支持的任何Clang版本。
140 BUG: KASAN: slab-out-of-bounds in kmalloc_oob_right+0xa8/0xbc [test_kasan]
143 CPU: 1 PID: 2760 Comm: insmod Not tainted 4.19.0-rc3+ #698
146 dump_stack+0x94/0xd8
147 print_address_description+0x73/0x280
148 kasan_report+0x144/0x187
149 __asan_report_store1_noabort+0x17/0x20
150 kmalloc_oob_right+0xa8/0xbc [test_kasan]
151 kmalloc_tests_init+0x16/0x700 [test_kasan]
152 do_one_initcall+0xa5/0x3ae
[all …]
/openbmc/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_xgmac.h12 #define X2_BLOCK_ETH_MAC_CSR_OFFSET 0x3000
13 #define BLOCK_AXG_MAC_OFFSET 0x0800
14 #define BLOCK_AXG_STATS_OFFSET 0x0800
15 #define BLOCK_AXG_MAC_CSR_OFFSET 0x2000
16 #define BLOCK_PCS_OFFSET 0x3800
18 #define XGENET_CONFIG_REG_ADDR 0x20
19 #define XGENET_SRST_ADDR 0x00
20 #define XGENET_CLKEN_ADDR 0x08
22 #define CSR_CLK BIT(0)
29 #define CSR_RST BIT(0)
[all …]

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