| /openbmc/linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-qmp-qserdes-txrx-v4_20.h | 10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88
11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90
13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
20 #define QSERDES_V4_20_RX_DFE_3 0x110
21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
[all …]
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | sama5_matrix.h | 13 u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */
14 u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */
15 u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
16 u32 res1[20]; /* 0x100 ~ 0x14c */
17 u32 meier; /* 0x150: Master Error Interrupt Enable Register */
18 u32 meidr; /* 0x154: Master Error Interrupt Disable Register */
19 u32 meimr; /* 0x158: Master Error Interrupt Mask Register */
20 u32 mesr; /* 0x15c: Master Error Status Register */
21 u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */
22 u32 res2[17]; /* 0x1A0 ~ 0x1E0 */
[all …]
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| /openbmc/linux/drivers/net/ethernet/sunplus/ |
| H A D | spl2sw_register.h | 10 #define L2SW_SW_INT_STATUS_0 0x0
11 #define L2SW_SW_INT_MASK_0 0x4
12 #define L2SW_FL_CNTL_TH 0x8
13 #define L2SW_CPU_FL_CNTL_TH 0xc
14 #define L2SW_PRI_FL_CNTL 0x10
15 #define L2SW_VLAN_PRI_TH 0x14
16 #define L2SW_EN_TOS_BUS 0x18
17 #define L2SW_TOS_MAP0 0x1c
18 #define L2SW_TOS_MAP1 0x20
19 #define L2SW_TOS_MAP2 0x24
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | fsl,imx8m-pinctrl.yaml | 81 reg = <0x30330000 0x10000>;
85 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
86 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
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| /openbmc/linux/include/linux/bcma/ |
| H A D | bcma_driver_gmac_cmn.h | 7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
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| /openbmc/linux/drivers/gpu/drm/ci/xfails/ |
| H A D | rockchip-rk3288-skips.txt | 14 # rockchip-drm display-subsystem: [drm] *ERROR* [CRTC:35:crtc-0] commit wait timed out
21 # CPU: 3 PID: 482 Comm: kms_plane_lowre Tainted: G W 5.19.0-rc2-323596-g00535de92171…
23 # Process kms_plane_lowre (pid: 482, stack limit = 0x1193ac2b)
24 # spin_dump from do_raw_spin_lock+0xa4/0xe8
25 # do_raw_spin_lock from wait_for_completion_timeout+0x2c/0x120
26 # wait_for_completion_timeout from drm_crtc_commit_wait+0x18/0x7c
27 # drm_crtc_commit_wait from drm_atomic_helper_wait_for_dependencies+0x44/0x168
28 # drm_atomic_helper_wait_for_dependencies from commit_tail+0x34/0x180
29 # commit_tail from drm_atomic_helper_commit+0x164/0x18c
30 # drm_atomic_helper_commit from drm_atomic_commit+0xac/0xe4
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpucfg.h | 17 u32 rst; /* base + 0x0 */
18 u32 ctrl; /* base + 0x4 */
19 u32 status; /* base + 0x8 */
20 u8 res[0x34]; /* base + 0xc */
24 u8 res0[0x40]; /* 0x000 */
25 struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */
26 u8 res1[0x44]; /* 0x140 */
27 u32 gen_ctrl; /* 0x184 */
28 u32 l2_status; /* 0x188 */
29 u8 res2[0x4]; /* 0x18c */
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/soc/imx/ |
| H A D | fsl,imx8mp-hdmi-blk-ctrl.yaml | 81 reg = <0x32fc0000 0x23c>;
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | imx6dl-pinfunc.h | 17 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
20 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
21 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
22 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
24 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
25 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
26 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6dl-pinfunc.h | 13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
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| H A D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
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| H A D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
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| H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
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| /openbmc/u-boot/include/ |
| H A D | fsl_sfp.h | 37 u32 ospr; /* 0x200 */
38 u32 ospr1; /* 0x204 */
40 u32 fswpr; /* 0x218 FSL Section Write Protect */
41 u32 fsl_uid; /* 0x21c FSL UID 0 */
42 u32 fsl_uid_1; /* 0x220 FSL UID 0 */
44 u32 srk_hash[8]; /* 0x254 Super Root Key Hash */
45 u32 oem_uid; /* 0x274 OEM UID 0*/
46 u32 oem_uid_1; /* 0x278 OEM UID 1*/
47 u32 oem_uid_2; /* 0x27c OEM UID 2*/
48 u32 oem_uid_3; /* 0x280 OEM UID 3*/
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra124/ |
| H A D | mc.h | 13 u32 reserved0[4]; /* offset 0x00 - 0x0C */
14 u32 mc_smmu_config; /* offset 0x10 */
15 u32 mc_smmu_tlb_config; /* offset 0x14 */
16 u32 mc_smmu_ptc_config; /* offset 0x18 */
17 u32 mc_smmu_ptb_asid; /* offset 0x1C */
18 u32 mc_smmu_ptb_data; /* offset 0x20 */
19 u32 reserved1[3]; /* offset 0x24 - 0x2C */
20 u32 mc_smmu_tlb_flush; /* offset 0x30 */
21 u32 mc_smmu_ptc_flush; /* offset 0x34 */
22 u32 reserved2[6]; /* offset 0x38 - 0x4C */
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra210/ |
| H A D | mc.h | 13 u32 reserved0[4]; /* offset 0x00 - 0x0C */
14 u32 mc_smmu_config; /* offset 0x10 */
15 u32 mc_smmu_tlb_config; /* offset 0x14 */
16 u32 mc_smmu_ptc_config; /* offset 0x18 */
17 u32 mc_smmu_ptb_asid; /* offset 0x1C */
18 u32 mc_smmu_ptb_data; /* offset 0x20 */
19 u32 reserved1[3]; /* offset 0x24 - 0x2C */
20 u32 mc_smmu_tlb_flush; /* offset 0x30 */
21 u32 mc_smmu_ptc_flush; /* offset 0x34 */
22 u32 reserved2[6]; /* offset 0x38 - 0x4C */
[all …]
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| /openbmc/u-boot/arch/arm/mach-zynqmp/include/mach/ |
| H A D | hardware.h | 10 #define ARASAN_NAND_BASEADDR 0xFF100000
12 #define ZYNQMP_TCM_BASE_ADDR 0xFFE00000
13 #define ZYNQMP_TCM_SIZE 0x40000
15 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
16 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
17 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
20 #define PS_MODE0 BIT(0)
31 #define RESET_REASON_EXTERNAL BIT(0)
35 u32 cpu_r5_ctrl; /* 0x90 */
37 u32 timestamp_ref_ctrl; /* 0x128 */
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | grf_rk322x.h | 33 unsigned int reserved2[(0x100 - 0x50) / 4 - 1];
38 unsigned int reserved3[(0x200 - 0x13c) / 4 - 1];
43 unsigned int reserved4[(0x400 - 0x23c) / 4 - 1];
45 unsigned int reserved5[(0x480 - 0x418) / 4 - 1];
48 unsigned int reserved6[(0x500 - 0x48c) / 4 - 1];
52 unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1];
54 unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
56 unsigned int reserved10[(0x680 - 0x604) / 4 - 1];
58 unsigned int reserved11[(0x690 - 0x684) / 4 - 1];
60 unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1];
[all …]
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| /openbmc/linux/sound/soc/fsl/ |
| H A D | fsl_audmix.h | 15 #define FSL_AUDMIX_CTR 0x200 /* Control */
16 #define FSL_AUDMIX_STR 0x204 /* Status */
18 #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
19 #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
20 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
21 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
22 #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
23 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
24 #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
26 #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
[all …]
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| /openbmc/linux/drivers/gpu/drm/bridge/ |
| H A D | nwl-dsi.h | 12 #define NWL_DSI_CFG_NUM_LANES 0x0
13 #define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4
14 #define NWL_DSI_CFG_T_PRE 0x8
15 #define NWL_DSI_CFG_T_POST 0xc
16 #define NWL_DSI_CFG_TX_GAP 0x10
17 #define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14
18 #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
19 #define NWL_DSI_CFG_HTX_TO_COUNT 0x1c
20 #define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20
21 #define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24
[all …]
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| /openbmc/linux/drivers/net/ethernet/mediatek/ |
| H A D | mtk_ppe_regs.h | 7 #define MTK_PPE_GLO_CFG 0x200
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
23 #define MTK_PPE_FLOW_CFG 0x204
42 #define MTK_PPE_IP_PROTO_CHK 0x208
43 #define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
46 #define MTK_PPE_TB_CFG 0x21c
47 #define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
63 #define MTK_PPE_BIND_LMT1 0x230
66 #define MTK_PPE_KEEPALIVE 0x234
86 #define MTK_PPE_TB_BASE 0x220
[all …]
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| /openbmc/u-boot/include/dt-bindings/pinctrl/ |
| H A D | pins-imx8mq.h | 24 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
25 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
26 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
27 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
28 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
29 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
30 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
31 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
32 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
33 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
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| /openbmc/linux/drivers/input/mouse/ |
| H A D | logibm.c | 31 #define LOGIBM_BASE 0x23c
34 #define LOGIBM_DATA_PORT LOGIBM_BASE + 0
39 #define LOGIBM_ENABLE_IRQ 0x00
40 #define LOGIBM_DISABLE_IRQ 0x10
41 #define LOGIBM_READ_X_LOW 0x80
42 #define LOGIBM_READ_X_HIGH 0xa0
43 #define LOGIBM_READ_Y_LOW 0xc0
44 #define LOGIBM_READ_Y_HIGH 0xe0
46 #define LOGIBM_DEFAULT_MODE 0x90
47 #define LOGIBM_CONFIG_BYTE 0x91
[all …]
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| H A D | inport.c | 29 #define INPORT_BASE 0x23c
32 #define INPORT_CONTROL_PORT INPORT_BASE + 0
36 #define INPORT_REG_BTNS 0x00
37 #define INPORT_REG_X 0x01
38 #define INPORT_REG_Y 0x02
39 #define INPORT_REG_MODE 0x07
40 #define INPORT_RESET 0x80
44 #define INPORT_VENDOR 0x0002
45 #define INPORT_SPEED_30HZ 0x01
46 #define INPORT_SPEED_50HZ 0x02
[all …]
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