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/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Drockchip,pinctrl.txt6 muxing options with option 0 being the use as a GPIO.
61 The MUX 0 means gpio and MUX 1 to N mean the specific device function.
81 reg = <0x20034000 0x100>;
108 reg = <0x20064000 0x400>;
116 pinctrl-0 = <&uart2_xfer>;
129 gpio0: gpio0@0x2000a000 {
131 reg = <0x2000a000 0x100>;
142 gpio1: gpio1@0x2003c000 {
144 reg = <0x2003c000 0x100>;
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Drockchip,gpio-bank.yaml66 reg = <0x2000a000 0x100>;
79 reg = <0x2003c000 0x100>;
/openbmc/u-boot/arch/arm/dts/
H A Drk3188.dtsi17 #size-cells = <0>;
20 cpu0: cpu@0 {
24 reg = <0x0>;
43 reg = <0x1>;
49 reg = <0x2>;
55 reg = <0x3>;
61 reg = <0x10080000 0x8000>;
64 ranges = <0 0x10080000 0x8000>;
66 smp-sram@0 {
68 reg = <0x0 0x50>;
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3066a.dtsi18 #size-cells = <0>;
21 cpu0: cpu@0 {
25 reg = <0x0>;
42 reg = <0x1>;
53 reg = <0x10080000 0x10000>;
56 ranges = <0 0x10080000 0x10000>;
58 smp-sram@0 {
60 reg = <0x0 0x50>;
66 reg = <0x1010c000 0x19c>;
81 #size-cells = <0>;
[all …]
H A Drk3188.dtsi18 #size-cells = <0>;
21 cpu0: cpu@0 {
25 reg = <0x0>;
35 reg = <0x1>;
43 reg = <0x2>;
51 reg = <0x3>;
57 cpu0_opp_table: opp-table-0 {
104 reg = <0x10080000 0x8000>;
107 ranges = <0 0x10080000 0x8000>;
109 smp-sram@0 {
[all …]