dts/rockchip/rk3066a.dtsi

18 		#size-cells = <0>;
21 		cpu0: cpu@0 {
25 			reg = <0x0>;
42 			reg = <0x1>;
53 		reg = <0x10080000 0x10000>;
56 		ranges = <0 0x10080000 0x10000>;
58 		smp-sram@0 {
60 			reg = <0x0 0x50>;
66 		reg = <0x1010c000 0x19c>;
81 			#size-cells = <0>;
83 			vop0_out_hdmi: endpoint@0 {
84 				reg = <0>;
92 		reg = <0x1010e000 0x19c>;
107 			#size-cells = <0>;
109 			vop1_out_hdmi: endpoint@0 {
110 				reg = <0>;
118 		reg = <0x10116000 0x2000>;
123 		pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
126 		#sound-dai-cells = <0>;
131 			#size-cells = <0>;
133 			hdmi_in: port@0 {
134 				reg = <0>;
136 				#size-cells = <0>;
138 				hdmi_in_vop0: endpoint@0 {
139 					reg = <0>;
157 		reg = <0x10118000 0x2000>;
160 		pinctrl-0 = <&i2s0_bus>;
167 		#sound-dai-cells = <0>;
173 		reg = <0x1011a000 0x2000>;
176 		pinctrl-0 = <&i2s1_bus>;
183 		#sound-dai-cells = <0>;
189 		reg = <0x1011c000 0x2000>;
192 		pinctrl-0 = <&i2s2_bus>;
199 		#sound-dai-cells = <0>;
205 		reg = <0x20000000 0x1000>;
223 		reg = <0x2000e000 0x100>;
231 		reg = <0x20010000 0x4000>;
238 			reg = <0x17 0x1>;
244 		reg = <0x20038000 0x100>;
252 		reg = <0x2003a000 0x100>;
260 		reg = <0x20060000 0x100>;
279 			reg = <0x20034000 0x100>;
292 			reg = <0x2003c000 0x100>;
305 			reg = <0x2003e000 0x100>;
318 			reg = <0x20080000 0x100>;
331 			reg = <0x20084000 0x100>;
344 			reg = <0x2000a000 0x100>;
404 				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
408 				rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
409 						<0 RK_PA2 1 &pcfg_pull_none>;
450 				rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
456 				rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
462 				rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
468 				rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
621 				rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>,
622 						<0 RK_PB0 1 &pcfg_pull_default>,
623 						<0 RK_PB1 1 &pcfg_pull_default>,
624 						<0 RK_PB2 1 &pcfg_pull_default>,
625 						<0 RK_PB3 1 &pcfg_pull_default>,
626 						<0 RK_PB4 1 &pcfg_pull_default>,
627 						<0 RK_PB5 1 &pcfg_pull_default>,
628 						<0 RK_PB6 1 &pcfg_pull_default>,
629 						<0 RK_PB7 1 &pcfg_pull_default>;
635 				rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
636 						<0 RK_PC1 1 &pcfg_pull_default>,
637 						<0 RK_PC2 1 &pcfg_pull_default>,
638 						<0 RK_PC3 1 &pcfg_pull_default>,
639 						<0 RK_PC4 1 &pcfg_pull_default>,
640 						<0 RK_PC5 1 &pcfg_pull_default>;
646 				rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>,
647 						<0 RK_PD1 1 &pcfg_pull_default>,
648 						<0 RK_PD2 1 &pcfg_pull_default>,
649 						<0 RK_PD3 1 &pcfg_pull_default>,
650 						<0 RK_PD4 1 &pcfg_pull_default>,
651 						<0 RK_PD5 1 &pcfg_pull_default>;
688 		#size-cells = <0>;
692 			reg = <0x17c>;
695 			#clock-cells = <0>;
696 			#phy-cells = <0>;
700 			reg = <0x188>;
703 			#clock-cells = <0>;
704 			#phy-cells = <0>;
711 	pinctrl-0 = <&i2c0_xfer>;
716 	pinctrl-0 = <&i2c1_xfer>;
721 	pinctrl-0 = <&i2c2_xfer>;
726 	pinctrl-0 = <&i2c3_xfer>;
731 	pinctrl-0 = <&i2c4_xfer>;
740 	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
747 	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
760 		#size-cells = <0>;
787 			#power-domain-cells = <0>;
797 			#power-domain-cells = <0>;
804 			#power-domain-cells = <0>;
811 	pinctrl-0 = <&pwm0_out>;
816 	pinctrl-0 = <&pwm1_out>;
821 	pinctrl-0 = <&pwm2_out>;
826 	pinctrl-0 = <&pwm3_out>;
831 	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
836 	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
841 	dmas = <&dmac1_s 0>, <&dmac1_s 1>;
844 	pinctrl-0 = <&uart0_xfer>;
852 	pinctrl-0 = <&uart1_xfer>;
860 	pinctrl-0 = <&uart2_xfer>;
868 	pinctrl-0 = <&uart3_xfer>;