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/openbmc/u-boot/arch/arm/mach-bcmstb/
H A DKconfig37 default 0x1f00000
/openbmc/linux/arch/sparc/include/asm/
H A Dobio.h3 * obio.h: Some useful locations in 0xFXXXXXXXX PA obio space on sun4d.
18 * | 0xFE | DEVID | | XDBUS ID | |
20 * 35 28 27 20 19 10 9 8 7 0
23 #define CSR_BASE_ADDR 0xe0000000
31 * | 0xF | DEVID[7:1] | |
33 * 35 32 31 25 24 0
36 #define ECSR_BASE_ADDR 0x00000000
44 #define BW_LOCAL_BASE 0xfff00000
46 #define BW_CID 0x00000000
47 #define BW_DBUS_CTRL 0x00000008
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/partitions/
H A Dbrcm,bcm4908-partitions.yaml33 "^partition@[0-9a-f]+$":
53 partition@0 {
55 reg = <0x0 0x100000>;
60 reg = <0x100000 0xf00000>;
65 reg = <0x1000000 0xf00000>;
70 reg = <0x1f00000 0x100000>;
/openbmc/u-boot/include/configs/
H A Dsyzygy_hub.h14 "fit_image=fit.itb\0" \
15 "bitstream_image=download.bit\0" \
16 "loadbit_addr=0x1000000\0" \
17 "load_addr=0x2000000\0" \
18 "fit_size=0x800000\0" \
19 "flash_off=0x100000\0" \
20 "nor_flash_off=0xE2100000\0" \
21 "fdt_high=0x20000000\0" \
22 "initrd_high=0x20000000\0" \
23 "loadbootenv_addr=0x2000000\0" \
[all …]
H A Dbcmstb.h47 * 0x0000 8000 vmlinux.bin.gz
49 * 0x01ef f000 FIT containing signed public key
51 * 0x01f0 0000 DTB copied from prior-stage-provided region
53 * 0x0200 0000 FIT containing ramdisk and device tree
59 * 0x0700 0000 Prior stage bootloader (PSB)
61 * 0x0761 7000 Prior-stage-provided device tree binary (DTB)
63 * 0x0f00 0000 Contiguous memory allocator (CMA/bmem) low address
65 * 0x8010 0000 U-Boot code at ELF load address
67 * 0xc000 0000 Top of RAM
75 * we set initrd_high and fdt_high to 0xffffffff, and the load and
[all …]
H A Dzynq-common.h23 # define CONFIG_SYS_PL310_BASE 0xf8f02000
26 #define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
29 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
48 # define CONFIG_SYS_FLASH_BASE 0xE2000000
66 # define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000
73 "${kernel_image} ram 0x3000000 0x500000\\\\;" \
74 "${devicetree_image} ram 0x2A00000 0x20000\\\\;" \
75 "${ramdisk_image} ram 0x2000000 0x600000\0" \
76 "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
77 "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dtpc0_qm_masks.h23 #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
H A Dnic0_qm0_masks.h23 #define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
H A Dmme0_qm_masks.h23 #define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
H A Ddma0_qm_masks.h23 #define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_edma0_qm_masks.h24 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
H A Dpdma0_qm_masks.h24 #define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_sdhci-test.c24 #define NPCM7XX_REG_SIZE 0x100
25 #define NPCM7XX_MMC_BA 0xF0842000
45 sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_APP_CMD); in setup_sd_card()
46 sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x41200000, 0, (41 << 8)); in setup_sd_card()
47 sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_ALL_SEND_CID); in setup_sd_card()
48 sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_SEND_RELATIVE_ADDR in setup_sd_card()
51 sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, rca << 16, 0, in setup_sd_card()
65 g_assert(fd >= 0); in write_sdread()
100 g_assert(fd >= 0); in sdwrite_read()
129 0, in test_reset()
[all …]
/openbmc/u-boot/drivers/net/
H A Dmtk_eth.h13 #define PDMA_BASE 0x0800
14 #define GDMA1_BASE 0x0500
15 #define GDMA2_BASE 0x1500
16 #define GMAC_BASE 0x10000
20 #define ETHSYS_SYSCFG0_REG 0x14
22 #define SYSCFG0_GE_MODE_M 0x3
24 #define ETHSYS_CLKCFG0_REG 0x2c
28 #define GE_MODE_RGMII 0
36 #define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10)
37 #define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10)
[all …]
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Drs90.dts16 reg = <0x0 0x2000000>;
26 reg = <0x1f00000 0x100000>;
42 pwms = <&pwm 3 40000 0>;
44 brightness-levels = <0 16 32 48 64 80 112 144 192 255>;
48 pinctrl-0 = <&pins_pwm3>;
53 keys@0 {
56 key-0 {
113 key@0 {
169 #phy-cells = <0>;
234 pinctrl-0 = <&pins_mmc1>;
[all …]
/openbmc/linux/drivers/input/joystick/
H A Dcobra.c26 …START, BTN_SELECT, BTN_TL, BTN_TR, BTN_X, BTN_Y, BTN_Z, BTN_A, BTN_B, BTN_C, BTN_TL2, BTN_TR2, 0 };
47 for (i = 0; i < 2; i++) { in cobra_read_packet()
48 r[i] = buf[i] = 0; in cobra_read_packet()
57 t[0]--; t[1]--; in cobra_read_packet()
59 for (i = 0, w = u ^ v; i < 2 && w; i++, w >>= 2) in cobra_read_packet()
60 if (w & 0x30) { in cobra_read_packet()
61 if ((w & 0x30) < 0x30 && r[i] < COBRA_LENGTH && t[i] > 0) { in cobra_read_packet()
65 } else t[i] = 0; in cobra_read_packet()
67 } while (t[0] > 0 || t[1] > 0); in cobra_read_packet()
71 ret = 0; in cobra_read_packet()
[all …]
/openbmc/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-npcm730-gsj.dts35 reg = <0 0x40000000>;
47 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
135 pinctrl-0 = <&spi0cs1_pins>;
138 flash@0 {
142 reg = <0>;
149 bmc@0{
151 reg = <0x000000 0x2000000>;
153 u-boot@0 {
155 reg = <0x0000000 0x80000>;
160 reg = <0x00100000 0x40000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8026-samsung-matisse-wifi.dts35 reg = <0x03200000 0x800000>;
88 pinctrl-0 = <&backlight_i2c_default_state>;
94 #size-cells = <0>;
98 reg = <0x2c>;
100 dev-ctrl = /bits/ 8 <0x80>;
101 init-brt = /bits/ 8 <0x3f>;
103 pwms = <&backlight_pwm 0 100000>;
107 rom-addr = /bits/ 8 <0xa0>;
108 rom-val = /bits/ 8 <0x44>;
112 rom-addr = /bits/ 8 <0xa1>;
[all …]
/openbmc/u-boot/doc/
H A DREADME.ae35057 MMC: mmc@f0e00000: 0
69 riscv32-unknown-linux-gnu-gcc (GCC) 7.2.0
79 RISC-V # fatls mmc 0:1
84 3 file(s), 0 dir(s)
86 RISC-V # sf probe 0:0 50000000 0
89 RISC-V # sf test 0x100000 0x1000
91 0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
96 0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
101 RISC-V # fatload mmc 0:1 0x600000 u-boot-ae350-32.bin
105 RISC-V # sf erase 0x0 0x51000
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
54 arm,psci-suspend-param = <0x0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
85 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
92 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
93 <0x0 0x1402000 0 0x2000>, /* GICC */
[all …]
H A Dfsl-ls1046a.dtsi38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
44 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 reg = <0x1>;
54 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
63 reg = <0x2>;
64 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
73 reg = <0x3>;
74 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls1043a.dtsi37 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0>;
49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
58 reg = <0x1>;
59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
68 reg = <0x2>;
69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
78 reg = <0x3>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
/openbmc/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_init_ops.c26 0,
27 0,
28 0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
29 0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
30 0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
31 0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
32 0x1d02, /* win 6: addr=0x1d02000, size=4096 bytes */
33 0x1d80, /* win 7: addr=0x1d80000, size=4096 bytes */
34 0x1d81, /* win 8: addr=0x1d81000, size=4096 bytes */
35 0x1d82, /* win 9: addr=0x1d82000, size=4096 bytes */
[all …]
/openbmc/linux/arch/mips/lantiq/xway/
H A Dsysctrl.c21 #define CGU_IFCCR 0x0018
22 #define CGU_IFCCR_VR9 0x0024
24 #define CGU_SYS 0x0010
26 #define CGU_PCICR 0x0034
27 #define CGU_PCICR_VR9 0x0038
29 #define CGU_EPHY 0x10
33 #define PMU_PWDCR 0x1C
35 #define PMU_PWDSR 0x20
37 #define PMU_PWDCR1 0x24
39 #define PMU_PWDSR1 0x28
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8994.dtsi29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
62 reg = <0x0 0x1>;
70 reg = <0x0 0x2>;
78 reg = <0x0 0x3>;
86 reg = <0x0 0x100>;
99 reg = <0x0 0x101>;
[all …]

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