Searched +full:0 +full:x1e789000 (Results 1 – 14 of 14) sorted by relevance
/openbmc/linux/Documentation/devicetree/bindings/soc/aspeed/ |
H A D | uart-routing.yaml | 46 reg = <0x1e789000 0x1000>; 50 ranges = <0x0 0x1e789000 0x1000>; 54 reg = <0x98 0x8>;
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/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/ |
H A D | platform.h | 18 #define ASPEED_SDRAM_CTRL 0x1e6e0000 19 #define ASPEED_HW_STRAP1 0x1e6e2070 20 #define ASPEED_REVISION_ID 0x1e6e207C 21 #define ASPEED_SYS_RESET_CTRL 0x1e6e203C 22 #define ASPEED_VGA_HANDSHAKE0 0x1e6e2040 /* VGA function handshake register */ 23 #define ASPEED_PCIE_CONFIG_SET 0x1e6e2180 24 #define ASPEED_DRAM_BASE 0x40000000 25 #define ASPEED_SRAM_BASE 0x1E720000 26 #define ASPEED_LPC_CTRL 0x1e789000 27 #define ASPEED_SRAM_SIZE 0x8000 [all …]
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/openbmc/linux/Documentation/devicetree/bindings/mfd/ |
H A D | aspeed-lpc.yaml | 16 peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The 60 "^lpc-ctrl@[0-9a-f]+$": 95 "^reset-controller@[0-9a-f]+$": 121 "^lpc-snoop@[0-9a-f]+$": 152 "^uart-routing@[0-9a-f]+$": 173 reg = <0x1e789000 0x1000>; 177 ranges = <0x0 0x1e789000 0x1000>; 181 reg = <0x80 0x80>; 189 reg = <0x98 0x4>; 195 reg = <0x90 0x8>; [all …]
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/openbmc/u-boot/board/aspeed/evb_ast2600/ |
H A D | evb_ast2600.c | 8 #define SCU_BASE 0x1e6e2000 9 #define ESPI_BASE 0x1e6ee000 10 #define LPC_BASE 0x1e789000 11 #define LPC_HICR5 (LPC_BASE + 0x80) 12 #define LPC_HICR6 (LPC_BASE + 0x84) 13 #define LPC_SNPWADR (LPC_BASE + 0x90) 14 #define LPC_HICRB (LPC_BASE + 0x100) 15 #define GPIO_BASE 0x1e780000 20 #define HICR5_SEL80HGIO (0x1f << 24) /* Select 80hGIO */ 21 #define SET_SEL80HGIO(x) ((x & 0x1f) << 24) /* Select 80hGIO Offset */ [all …]
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/openbmc/u-boot/board/aspeed/ast2600_dcscm/ |
H A D | ast2600_dcscm.c | 8 #define SCU_BASE 0x1e6e2000 9 #define ESPI_BASE 0x1e6ee000 10 #define LPC_BASE 0x1e789000 11 #define LPC_HICR5 (LPC_BASE + 0x80) 12 #define LPC_HICR6 (LPC_BASE + 0x84) 13 #define LPC_SNPWADR (LPC_BASE + 0x90) 14 #define LPC_HICRB (LPC_BASE + 0x100) 15 #define GPIO_BASE 0x1e780000 20 #define HICR5_SEL80HGIO (0x1f << 24) /* Select 80hGIO */ 21 #define SET_SEL80HGIO(x) ((x & 0x1f) << 24) /* Select 80hGIO Offset */ [all …]
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/openbmc/u-boot/board/aspeed/ast2600_intel/ |
H A D | intel.c | 9 #define SCU_BASE 0x1e6e2000 10 #define SCU_PINMUX4 (SCU_BASE + 0x410) 12 #define SCU_PINMUX5 (SCU_BASE + 0x414) 17 #define SCU_GPIO_PD0 (SCU_BASE + 0x610) 19 #define SCU_PINMUX27 (SCU_BASE + 0x69c) 23 #define ESPI_BASE 0x1e6ee000 24 #define ESPI_CTRL (ESPI_BASE + 0x0) 25 #define ESPI_INT_EN (ESPI_BASE + 0xc) 26 #define ESPI_CTRL2 (ESPI_BASE + 0x80) 27 #define ESPI_SYSEVT_INT_EN (ESPI_BASE + 0x94) [all …]
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/openbmc/qemu/hw/arm/ |
H A D | aspeed_ast2400.c | 26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 29 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 30 [ASPEED_DEV_IOMEM] = 0x1E600000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 34 [ASPEED_DEV_UHCI] = 0x1E6B0000, 35 [ASPEED_DEV_VIC] = 0x1E6C0000, 36 [ASPEED_DEV_SDMC] = 0x1E6E0000, 37 [ASPEED_DEV_SCU] = 0x1E6E2000, [all …]
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H A D | aspeed_ast2600.c | 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 25 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 26 [ASPEED_DEV_SRAM] = 0x10000000, 27 [ASPEED_DEV_DPMCU] = 0x18000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_DEV_IOMEM] = 0x1E600000, 30 [ASPEED_DEV_PWM] = 0x1E610000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | ast2400.dtsi | 39 #size-cells = <0>; 41 cpu@0 { 44 reg = <0>; 50 reg = <0x40000000 0>; 60 reg = < 0x1e620000 0xc4 61 0x20000000 0x10000000 >; 63 #size-cells = <0>; 69 flash@0 { 70 reg = < 0 >; 87 reg = < 0x1e630000 0xc4 [all …]
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H A D | ast2500.dtsi | 39 #size-cells = <0>; 41 cpu@0 { 44 reg = <0>; 50 reg = <0x80000000 0>; 60 reg = < 0x1e620000 0xc4 61 0x20000000 0x10000000 >; 63 #size-cells = <0>; 69 flash@0 { 70 reg = < 0 >; 87 reg = < 0x1e630000 0xc4 [all …]
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H A D | ast2600.dtsi | 47 #size-cells = <0>; 50 cpu@0 { 53 reg = <0>; 79 size = <0x01000000>; 80 alignment = <0x01000000>; 86 size = <0x04000000>; 87 alignment = <0x01000000>; 106 reg = <0x40461000 0x1000>, 107 <0x40462000 0x1000>, 108 <0x40464000 0x2000>, [all …]
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/openbmc/linux/arch/arm/boot/dts/aspeed/ |
H A D | aspeed-g4.dtsi | 36 #size-cells = <0>; 38 cpu@0 { 41 reg = <0>; 47 reg = <0x40000000 0>; 57 reg = <0x1e620000 0x94>, <0x20000000 0x10000000>; 59 #size-cells = <0>; 64 flash@0 { 65 reg = < 0 >; 102 reg = <0x1e630000 0x18>, <0x30000000 0x10000000>; 104 #size-cells = <0>; [all …]
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H A D | aspeed-g6.dtsi | 48 #size-cells = <0>; 54 reg = <0xf00>; 60 reg = <0xf01>; 78 reg = <0x1e6e0000 0x174>; 79 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 95 reg = <0x40461000 0x1000>, 96 <0x40462000 0x1000>, 97 <0x40464000 0x2000>, 98 <0x40466000 0x2000>; 103 reg = <0x1e600000 0x100>; [all …]
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H A D | aspeed-g5.dtsi | 37 #size-cells = <0>; 39 cpu@0 { 42 reg = <0>; 48 reg = <0x80000000 0>; 58 reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; 60 #size-cells = <0>; 65 flash@0 { 66 reg = < 0 >; 89 reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>; 91 #size-cells = <0>; [all …]
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