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/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dboard_common.c33 #define PHY_RESET_MASK (BIT(GRP_F + 0) | BIT(GRP_F + 2)) in reset_eth_phy()
35 u32 value = readl(0x1e780020); in reset_eth_phy()
36 u32 direction = readl(0x1e780024); in reset_eth_phy()
42 writel(direction, 0x1e780024); in reset_eth_phy()
43 writel(value, 0x1e780020); in reset_eth_phy()
44 while((readl(0x1e780020) & PHY_RESET_MASK) != 0); in reset_eth_phy()
49 writel(value, 0x1e780020); in reset_eth_phy()
50 while((readl(0x1e780020) & PHY_RESET_MASK) != PHY_RESET_MASK); in reset_eth_phy()
66 if (rev_id == 0x0501030305010303 || rev_id == 0x0501020305010203) { in board_init()
68 tmp_val = readl(0x1e60008c) & (~BIT(0)); in board_init()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Daspeed,ast2600-ahbc.yaml36 reg = <0x1e600000 0x100>;
/openbmc/openbmc/meta-facebook/meta-yosemitev2/recipes-bsp/u-boot/u-boot-aspeed-sdk/
H A D0001-board-aspeed-Add-Mux-for-yosemitev2.patch16 ldr r2, =0x00000800
20 + ldr r0, =0x1e780024
22 + orr r1, r1, #0xF
25 + ldr r0, =0x1e780020
27 + and r1, r1, #0xFFFFFFF0
28 + orr r1, r1, #0xC
35 + ldr r0, =0x1e6e2080
37 + ldr r2, =0xBFBFFFFF
41 + ldr r0, =0x1e6e2084
45 + // Enable GPIOE[0-3] Tolerant
[all …]
/openbmc/qemu/hw/arm/
H A Daspeed_ast2400.c26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
29 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
30 [ASPEED_DEV_IOMEM] = 0x1E600000,
31 [ASPEED_DEV_FMC] = 0x1E620000,
32 [ASPEED_DEV_SPI1] = 0x1E630000,
33 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
34 [ASPEED_DEV_UHCI] = 0x1E6B0000,
35 [ASPEED_DEV_VIC] = 0x1E6C0000,
36 [ASPEED_DEV_SDMC] = 0x1E6E0000,
37 [ASPEED_DEV_SCU] = 0x1E6E2000,
[all …]
H A Daspeed_ast2600.c21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000
25 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
26 [ASPEED_DEV_SRAM] = 0x10000000,
27 [ASPEED_DEV_DPMCU] = 0x18000000,
28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
29 [ASPEED_DEV_IOMEM] = 0x1E600000,
30 [ASPEED_DEV_PWM] = 0x1E610000,
31 [ASPEED_DEV_FMC] = 0x1E620000,
32 [ASPEED_DEV_SPI1] = 0x1E630000,
[all …]
/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_dbg.h32 __be16 risc_ram[0xf800];
33 __be16 stack_ram[0x1000];
54 __be16 risc_ram[0xf000];
86 __be32 code_ram[0x2000];
125 __be32 code_ram[0x2000];
164 __be32 code_ram[0x2000];
212 __be32 code_ram[0x2400];
217 #define EFT_BYTES_PER_BUFFER 0x4000
221 #define FCE_BYTES_PER_BUFFER 0x400
255 #define TYPE_REQUEST_QUEUE 0x1
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/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-g6.dtsi48 #size-cells = <0>;
54 reg = <0xf00>;
60 reg = <0xf01>;
78 reg = <0x1e6e0000 0x174>;
79 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
95 reg = <0x40461000 0x1000>,
96 <0x40462000 0x1000>,
97 <0x40464000 0x2000>,
98 <0x40466000 0x2000>;
103 reg = <0x1e600000 0x100>;
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dplatform.S34 * V2 |2014.10.31 : 1.[P2] Enable VGA wide screen support (SCU40[0]=1)
63 * |2016.07.12 : 2.[P1] Modify DDR4 read path ODT from 60 ohm to 48 ohm, at address 0x1e6e0204
64 … | : 3.[P1] Modify DDR4 Ron calibration to manual mode to fix Vix issue, set Ron_pu = 0
120 #define ASTMMC_INIT_VER 0x12 @ 8bit verison number
121 #define ASTMMC_INIT_DATE 0x20171027 @ Release date
133 //#define ASTMMC_DDR4_MANUAL_RPU 0x0 @ 0x0-0xF, larger value means weaker driving
134 //#define ASTMMC_DDR4_MANUAL_RPD 0x0 @ 0x0-0xF, larger value means stronger driving
157 #define ASTMMC_REGIDX_010 0x00
158 #define ASTMMC_REGIDX_014 0x04
159 #define ASTMMC_REGIDX_018 0x08
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/openbmc/linux/drivers/fsi/
H A Dfsi-master-ast-cf.c31 #define SCU_COPRO_CTRL 0x100
32 #define SCU_COPRO_RESET 0x00000002
33 #define SCU_COPRO_CLK_EN 0x00000001
36 #define SCU_2500_COPRO_SEG0 0x104
37 #define SCU_2500_COPRO_SEG1 0x108
38 #define SCU_2500_COPRO_SEG2 0x10c
39 #define SCU_2500_COPRO_SEG3 0x110
40 #define SCU_2500_COPRO_SEG4 0x114
41 #define SCU_2500_COPRO_SEG5 0x118
42 #define SCU_2500_COPRO_SEG6 0x11c
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dast2600.dtsi47 #size-cells = <0>;
50 cpu@0 {
53 reg = <0>;
79 size = <0x01000000>;
80 alignment = <0x01000000>;
86 size = <0x04000000>;
87 alignment = <0x01000000>;
106 reg = <0x40461000 0x1000>,
107 <0x40462000 0x1000>,
108 <0x40464000 0x2000>,
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/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_post.c40 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
41 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
51 for (i = 0x81; i <= 0x9f; i++) in ast_set_def_ext_reg()
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); in ast_set_def_ext_reg()
59 index = 0xa0; in ast_set_def_ext_reg()
60 while (*ext_reg_info != 0xff) { in ast_set_def_ext_reg()
61 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); in ast_set_def_ext_reg()
67 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */ in ast_set_def_ext_reg()
70 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); in ast_set_def_ext_reg()
71 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); in ast_set_def_ext_reg()
[all …]