Lines Matching +full:0 +full:x1e600000
34 * V2 |2014.10.31 : 1.[P2] Enable VGA wide screen support (SCU40[0]=1)
63 * |2016.07.12 : 2.[P1] Modify DDR4 read path ODT from 60 ohm to 48 ohm, at address 0x1e6e0204
64 … | : 3.[P1] Modify DDR4 Ron calibration to manual mode to fix Vix issue, set Ron_pu = 0
120 #define ASTMMC_INIT_VER 0x12 @ 8bit verison number
121 #define ASTMMC_INIT_DATE 0x20171027 @ Release date
133 //#define ASTMMC_DDR4_MANUAL_RPU 0x0 @ 0x0-0xF, larger value means weaker driving
134 //#define ASTMMC_DDR4_MANUAL_RPD 0x0 @ 0x0-0xF, larger value means stronger driving
157 #define ASTMMC_REGIDX_010 0x00
158 #define ASTMMC_REGIDX_014 0x04
159 #define ASTMMC_REGIDX_018 0x08
160 #define ASTMMC_REGIDX_020 0x0C
161 #define ASTMMC_REGIDX_024 0x10
162 #define ASTMMC_REGIDX_02C 0x14
163 #define ASTMMC_REGIDX_030 0x18
164 #define ASTMMC_REGIDX_214 0x1C
165 #define ASTMMC_REGIDX_2E0 0x20
166 #define ASTMMC_REGIDX_2E4 0x24
167 #define ASTMMC_REGIDX_2E8 0x28
168 #define ASTMMC_REGIDX_2EC 0x2C
169 #define ASTMMC_REGIDX_2F0 0x30
170 #define ASTMMC_REGIDX_2F4 0x34
171 #define ASTMMC_REGIDX_2F8 0x38
172 #define ASTMMC_REGIDX_RFC 0x3C
173 #define ASTMMC_REGIDX_PLL 0x40
176 .word 0x53503C37 @ 0x010
177 .word 0xF858D47F @ 0x014
178 .word 0x00010000 @ 0x018
179 .word 0x00000000 @ 0x020
180 .word 0x00000000 @ 0x024
181 .word 0x02101C60 @ 0x02C
182 .word 0x00000040 @ 0x030
183 .word 0x00000020 @ 0x214
184 .word 0x02001000 @ 0x2E0
185 .word 0x0C000085 @ 0x2E4
186 .word 0x000BA018 @ 0x2E8
187 .word 0x2CB92104 @ 0x2EC
188 .word 0x07090407 @ 0x2F0
189 .word 0x81000700 @ 0x2F4
190 .word 0x0C400800 @ 0x2F8
191 .word 0x7F5E3A27 @ tRFC
192 .word 0x00005B80 @ PLL
194 .word 0x64604D38 @ 0x010
195 .word 0x29690599 @ 0x014
196 .word 0x00000300 @ 0x018
197 .word 0x00000000 @ 0x020
198 .word 0x00000000 @ 0x024
199 .word 0x02181E70 @ 0x02C
200 .word 0x00000040 @ 0x030
201 .word 0x00000024 @ 0x214
202 .word 0x02001300 @ 0x2E0
203 .word 0x0E0000A0 @ 0x2E4
204 .word 0x000E001B @ 0x2E8
205 .word 0x35B8C105 @ 0x2EC
206 .word 0x08090408 @ 0x2F0
207 .word 0x9B000800 @ 0x2F4
208 .word 0x0E400A00 @ 0x2F8
209 .word 0x9971452F @ tRFC
210 .word 0x000071C1 @ PLL
213 .word 0x53503D26 @ 0x010
214 .word 0xE878D87F @ 0x014
215 .word 0x00019000 @ 0x018
216 .word 0x08000000 @ 0x020
217 .word 0x00000400 @ 0x024
218 .word 0x00000200 @ 0x02C
219 .word 0x00000101 @ 0x030
220 .word 0x00000020 @ 0x214
221 .word 0x03002200 @ 0x2E0
222 .word 0x0C000085 @ 0x2E4
223 .word 0x000BA01A @ 0x2E8
224 .word 0x2CB92106 @ 0x2EC
225 .word 0x07060606 @ 0x2F0
226 .word 0x81000700 @ 0x2F4
227 .word 0x0C400800 @ 0x2F8
228 .word 0x7F5E3A3A @ tRFC
229 .word 0x00005B80 @ PLL
231 .word 0x63604E37 @ 0x010
232 .word 0xE97AFA99 @ 0x014
233 .word 0x00019000 @ 0x018
234 .word 0x08000000 @ 0x020
235 .word 0x00000400 @ 0x024
236 .word 0x00000410 @ 0x02C
238 .word 0x00000501 @ 0x030 @ ODT = 48 ohm
240 .word 0x00000101 @ 0x030 @ ODT = 60 ohm
242 .word 0x00000024 @ 0x214
243 .word 0x03002900 @ 0x2E0
244 .word 0x0E0000A0 @ 0x2E4
245 .word 0x000E001C @ 0x2E8
246 .word 0x35B8C106 @ 0x2EC
247 .word 0x08080607 @ 0x2F0
248 .word 0x9B000900 @ 0x2F4
249 .word 0x0E400A00 @ 0x2F8
250 .word 0x99714545 @ tRFC
251 .word 0x000071C1 @ PLL
254 ldr r0, =0x1e782024 @ Set Timer3 Reload
257 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
258 ldr r1, =0x00040000
261 ldr r0, =0x1e782030 @ Enable Timer3
266 ldr r0, =0x1e6c0090 @ Check ISR for Timer3 timeout
271 bic r1, r1, #0xFFFBFFFF
273 cmp r2, #0x01
277 ldr r0, =0x1e78203C @ Disable Timer3
278 mov r2, #0xF
282 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
283 ldr r1, =0x00040000
288 ldr r0, =0x1e620084
289 ldr r1, =0x20010000
291 ldr r0, =0x1e62008C
292 ldr r1, =0x20000200
294 ldr r0, =0x1e620080
295 ldr r1, =0x0000000D
298 and r2, r6, #0xF
301 ldr r0, =0x1e620008
302 ldr r2, =0x00000800
306 and r1, r1, #0xF
308 addgt r1, r1, #0x37
309 addle r1, r1, #0x30
325 ldr r0, =0x1e600000
326 ldr r1, =0xAEED1A03
328 ldr r0, =0x1e600084
329 ldr r1, =0x00010000
331 add r0, r0, #0x4
332 mov r1, #0x0
335 ldr r0, =0x1e6e2000
336 ldr r1, =0x1688a8a8
340 ldr r0, =0x1e6e2070 @ check fast reset flag
341 ldr r2, =0x08000000
346 ldr r0, =0x1e785010
348 cmp r3, #0x0
350 add r0, r0, #0x04
351 mov r3, #0x77
353 ldr r0, =0x1e720004 @ Copy initial strap register to 0x1e720004
355 add r0, r0, #0x04 @ Copy initial strap register to 0x1e720008
357 add r0, r0, #0x04 @ Copy initial strap register to 0x1e72000c
359 ldr r0, =0x1e6e207c @ clear fast reset flag
361 ldr r0, =0x1e6e203c @ clear watchdog reset flag
363 and r1, r1, #0x01
365 ldr r0, =0x1e78501c @ restore normal mask setting
366 ldr r1, =0x023FFFF3 @ added 2016.09.06
372 ldr r0, =0x1e785004
373 ldr r1, =0x00000001
375 ldr r0, =0x1e785008
376 ldr r1, =0x00004755
378 ldr r0, =0x1e78500c @ enable Full reset
379 ldr r1, =0x00000033
383 mov r2, #0 @ set r2 = 0, freezed
384 ldr r0, =0x1e787008
385 mov r1, #0x7
387 ldr r0, =0x1e78700c
388 mov r1, #0x3
390 ldr r0, =0x1e787020
392 ldr r0, =0x1e787034
394 ldr r0, =0x1e787004
396 ldr r0, =0x1e787010
398 ldr r0, =0x1e78701c
400 ldr r0, =0x1e787014 @ read clear
402 ldr r0, =0x1e787018 @ read clear
404 ldr r0, =0x1e787008 @ read clear
406 ldr r0, =0x1e78301c @ read clear
408 ldr r0, =0x1e78d01c @ read clear
410 ldr r0, =0x1e78e01c @ read clear
412 ldr r0, =0x1e78f01c @ read clear
414 ldr r0, =0x1e788020
416 ldr r0, =0x1e788034
418 ldr r0, =0x1e78800c
420 ldr r0, =0x1e789008
422 ldr r0, =0x1e789010
423 mov r1, #0x40
425 ldr r0, =0x1e789024 @ read clear
427 ldr r0, =0x1e789028 @ read clear
429 ldr r0, =0x1e78902c @ read clear
431 ldr r0, =0x1e789114 @ read clear
433 ldr r0, =0x1e789124 @ read clear
435 ldr r0, =0x1e78903c
437 ldr r0, =0x1e789040
439 ldr r0, =0x1e789044
441 ldr r0, =0x1e78911c
443 ldr r0, =0x1e78912c
444 ldr r1, =0x200
446 ldr r0, =0x1e789104
447 ldr r1, =0xcc00
449 ldr r0, =0x1e789108
451 ldr r0, =0x1e78910c
452 ldr r1, =0x1f0
454 ldr r0, =0x1e789170
456 ldr r0, =0x1e789174
458 ldr r0, =0x1e7890a0
459 ldr r1, =0xff00
461 ldr r0, =0x1e7890a4
463 ldr r0, =0x1e789080
464 ldr r1, =0x400
466 ldr r0, =0x1e789084
467 ldr r1, =0x0001000f
469 ldr r0, =0x1e789088
470 ldr r1, =0x3000fff8
472 ldr r0, =0x1e78908c
473 ldr r1, =0xfff8f007
475 ldr r0, =0x1e789098
476 ldr r1, =0x00000a30
478 ldr r0, =0x1e78909c
480 ldr r0, =0x1e789100
482 ldr r0, =0x1e789130
483 ldr r1, =0x00000080
485 ldr r0, =0x1e789138
486 ldr r1, =0x00010198
488 ldr r0, =0x1e789140
489 ldr r1, =0x0000a000
491 ldr r0, =0x1e789158
492 ldr r1, =0x00000080
494 ldr r0, =0x1e789180
495 ldr r1, =0xb6db1bff
497 ldr r0, =0x1e789184
499 ldr r0, =0x1e789188
501 ldr r0, =0x1e78918c
503 ldr r0, =0x1e789190
504 ldr r1, =0x05020100
506 ldr r0, =0x1e789194
507 ldr r1, =0x07000706
509 ldr r0, =0x1e789198
511 ldr r0, =0x1e78919c
512 ldr r1, =0x30
514 ldr r0, =0x1e7891a0
515 ldr r1, =0x00008100
517 ldr r0, =0x1e7891a4
518 ldr r1, =0x2000
520 ldr r0, =0x1e7891a8
521 ldr r1, =0x3ff
523 ldr r0, =0x1e7891ac
525 ldr r0, =0x1e789240
526 mov r1, #0xff
528 ldr r0, =0x1e789244
530 ldr r0, =0x1e789248
531 mov r1, #0x80
533 ldr r0, =0x1e789250
535 ldr r0, =0x1e789254
539 …ldr r0, =0x1e62009c @ clear software strap flag for doing again after res…
540 ldr r1, =0xAEEDFC20
542 ldr r0, =0x1e785004
543 ldr r1, =0x00000001
545 ldr r0, =0x1e785008
546 ldr r1, =0x00004755
548 ldr r0, =0x1e78501c @ enable full mask of SOC reset
549 ldr r1, =0x03FFFFFF @ added 2016.09.06
551 ldr r0, =0x1e78500c @ enable SOC reset
552 ldr r1, =0x00000013
564 ldr r0, =0x1e782038
565 mov r1, #0xAE
569 ldr r0, =0x1e78203c
570 ldr r1, =0x0000F000
573 ldr r0, =0x1e782044
574 ldr r1, =0xFFFFFFFF
577 ldr r0, =0x1e782030
584 ldr r0, =0x1e6e2000
585 ldr r1, =0x1688a8a8
588 ldr r0, =0x1e6e2040
590 orr r1, r1, #0x80
594 ldr r0, =0x1e6e2070
596 ldr r0, =0x1e6e207c
597 ldr r2, =0x02000000
598 ldr r3, =0x00004000
603 ldr r0, =0x1e6e200c @ enable portA clock
604 ldr r2, =0x00004000
608 ldr r0, =0x1e6e2090 @ set portA as host mode
609 ldr r1, =0x2000A000
611 ldr r0, =0x1e6e2094 @ set portB as host mode
612 ldr r1, =0x00004000
614 ldr r0, =0x1e6e2070
615 ldr r2, =0x00800000
619 ldr r0, =0x1e6e207c
624 ldr r2, =0x000003E8 @ Set Timer3 Reload = 1 ms
632 ldr r0, =0x1e6e2070
633 ldr r1, =0x00800000
638 ldr r0, =0x00000016
639 mrc p15, 0, r1, c15, c2, 4
640 mcr p15, 0, r0, c15, c2, 4
647 ldr r0, =0x1e78502c
648 mov r1, #0
655 ldr r0, =0x1e78504c
656 mov r1, #0
659 ldr r0, =0x1e6e0000
660 ldr r1, =0xFC600309
668 ldr r0, =0x1e6e2040
670 bic r1, r1, #0xFFFFFFBF
672 cmp r2, #0x01
676 ldr r0, =0x1e6e202c
678 orr r1, r1, #0x40
681 ldr r0, =0x1e6e2070 @ Load strap register
686 ldr r2, =0xC48066C0 @ load PLL parameter for 24Mhz CLKIN (330)
688 ldr r2, =0x93002400 @ load PLL parameter for 24Mhz CLKIN (396)
691 tst r1, #0x01
694 ldr r2, =0x930023E0 @ load PLL parameter for 24Mhz CLKIN (384)
696 ldr r2, =0x930023C0 @ load PLL parameter for 24Mhz CLKIN (372)
698 ldr r2, =0x930023A0 @ load PLL parameter for 24Mhz CLKIN (360)
705 tst r1, #0x01
708 ldr r2, =0xC4806680 @ load PLL parameter for 25Mhz CLKIN (331)
710 ldr r2, =0x930023E0 @ load PLL parameter for 25Mhz CLKIN (400)
713 tst r1, #0x01
716 ldr r2, =0x930023C0 @ load PLL parameter for 24Mhz CLKIN (387.5)
718 ldr r2, =0x930023A0 @ load PLL parameter for 24Mhz CLKIN (375)
720 ldr r2, =0x93002380 @ load PLL parameter for 24Mhz CLKIN (362.5)
725 ldr r0, =0x1e6e2160 @ set 24M Jitter divider (HPLL=825MHz)
726 ldr r1, =0x00011320
730 ldr r0, =0x1e6e2020 @ M-PLL (DDR SDRAM) Frequency
736 ldr r2, =0x00000BB8 @ Set Timer3 Reload = 3 ms
746 ldr r0, =0x1e78505c
747 ldr r1, =0x00000004
749 ldr r0, =0x1e785044
750 ldr r1, =0x00000001
752 ldr r0, =0x1e785048
753 ldr r1, =0x00004755
755 ldr r0, =0x1e78504c
756 ldr r1, =0x00000013
760 tst r1, #0x02
763 ldr r0, =0x1e78505c
764 ldr r1, =0x023FFFF3
766 ldr r0, =0x1e785044
767 ldr r1, =0x000F4240
769 ldr r0, =0x1e785048
770 ldr r1, =0x00004755
772 ldr r0, =0x1e785054
773 ldr r1, =0x00000077
776 ldr r0, =0x1e6e0000
777 ldr r1, =0xFC600309
781 cmp r2, #0x1
784 ldr r0, =0x1e6e0034 @ disable MMC request
785 ldr r1, =0x00020000
789 ldr r2, =0x00002710 @ Set Timer3 Reload = 10 ms
799 ldr r0, =0x1e78909c @ route UART5 to UART Port1, 2016.08.29
800 ldr r1, =0x10000004
803 ldr r0, =0x1e6e2084
805 mov r2, #0xC0 @ Enable pinmux of TXD1/RXD1
810 ldr r0, =0x1e78400c
811 mov r1, #0x83
814 ldr r0, =0x1e6e202c
817 tst r2, #0x01
818 ldr r0, =0x1e784000
819 moveq r1, #0x0D @ Baudrate 115200
820 movne r1, #0x01 @ Baudrate 115200, div13
822 moveq r1, #0x27 @ Baudrate 38400
823 movne r1, #0x03 @ Baudrate 38400 , div13
827 ldr r0, =0x1e784004
828 mov r1, #0x00
831 ldr r0, =0x1e78400c
832 mov r1, #0x03
835 ldr r0, =0x1e784008
836 mov r1, #0x07
839 ldr r0, =0x1e784000
840 mov r1, #0x0D @ '\r'
842 mov r1, #0x0A @ '\n'
844 mov r1, #0x44 @ 'D'
846 mov r1, #0x52 @ 'R'
848 mov r1, #0x41 @ 'A'
850 mov r1, #0x4D @ 'M'
852 mov r1, #0x20 @ ' '
854 mov r1, #0x49 @ 'I'
856 mov r1, #0x6E @ 'n'
858 mov r1, #0x69 @ 'i'
860 mov r1, #0x74 @ 't'
862 mov r1, #0x2D @ '-'
864 mov r1, #0x56 @ 'V'
871 mov r1, #0x2D @ '-'
873 ldr r0, =0x1e784014
876 tst r1, #0x40
878 ldr r0, =0x1e784000
879 mov r1, #0x44 @ 'D'
881 mov r1, #0x44 @ 'D'
883 mov r1, #0x52 @ 'R'
890 ldr r0, =0x1e6e0034 @ disable SDRAM reset
891 ldr r1, =0x00020080
894 ldr r0, =0x1e6e0008
895 ldr r1, =0x2003000F /* VGA */
898 …ldr r0, =0x1e6e0038 @ disable all DRAM requests except CPU during PHY init
899 ldr r1, =0xFFFFEBFF
902 ldr r0, =0x1e6e0040
903 ldr r1, =0x88448844
906 ldr r0, =0x1e6e0044
907 ldr r1, =0x24422288
910 ldr r0, =0x1e6e0048
911 ldr r1, =0x22222222
914 ldr r0, =0x1e6e004c
915 ldr r1, =0x22222222
918 ldr r0, =0x1e6e0050
919 ldr r1, =0x80000000
922 ldr r1, =0x00000000
923 ldr r0, =0x1e6e0208 @ PHY Setting
925 ldr r0, =0x1e6e0218
927 ldr r0, =0x1e6e0220
929 ldr r0, =0x1e6e0228
931 ldr r0, =0x1e6e0230
933 ldr r0, =0x1e6e02a8
935 ldr r0, =0x1e6e02b0
938 ldr r0, =0x1e6e0240
939 ldr r1, =0x86000000
942 ldr r0, =0x1e6e0244
943 ldr r1, =0x00008600
946 ldr r0, =0x1e6e0248
947 ldr r1, =0x80000000
950 ldr r0, =0x1e6e024c
951 ldr r1, =0x80808080
955 ldr r0, =0x1e6e2070
957 ldr r2, =0x01000000 @ bit[24]=1 => DDR4
968 ldr r0, =0x1e784000
969 mov r1, #0x33 @ '3'
971 mov r1, #0x0D @ '\r'
973 mov r1, #0x0A @ '\n'
983 ldr r0, =0x1e6e0004
985 ldr r1, =0x00000323 @ Init to 8GB stack
987 ldr r1, =0x00000303 @ Init to 8GB
991 ldr r0, =0x1e6e0010
995 ldr r0, =0x1e6e0014
999 ldr r0, =0x1e6e0018
1004 ldr r0, =0x1e6e0020 @ MRS_4/6
1008 ldr r0, =0x1e6e0024 @ MRS_5
1012 ldr r0, =0x1e6e002c @ MRS_0/2
1014 mov r2, #0x1
1018 ldr r0, =0x1e6e0030 @ MRS_1/3
1023 ldr r0, =0x1e6e0200
1024 ldr r1, =0x02492AAE
1027 ldr r0, =0x1e6e0204
1029 ldr r1, =0x10001001
1031 ldr r1, =0x00001001
1035 ldr r0, =0x1e6e020c
1036 ldr r1, =0x55E00B0B
1039 ldr r0, =0x1e6e0210
1040 ldr r1, =0x20000000
1043 ldr r0, =0x1e6e0214
1047 ldr r0, =0x1e6e02e0
1051 ldr r0, =0x1e6e02e4
1055 ldr r0, =0x1e6e02e8
1059 ldr r0, =0x1e6e02ec
1063 ldr r0, =0x1e6e02f0
1067 ldr r0, =0x1e6e02f4
1071 ldr r0, =0x1e6e02f8
1075 ldr r0, =0x1e6e0290
1076 ldr r1, =0x00100008
1079 ldr r0, =0x1e6e02c0
1080 ldr r1, =0x00000006
1084 ldr r0, =0x1e6e0060 @ Fire DDRPHY Init
1085 ldr r1, =0x00000005
1088 ldr r0, =0x1e6e0034
1089 ldr r1, =0x00020091
1093 ldr r0, =0x1e784000
1094 mov r1, #0x30 @ '0'
1098 ldr r0, =0x1e6e0120
1099 mov r1, #0x00
1108 ldr r0, =0x1e6e03a0 @ check Gate Training Pass Window
1110 ldr r2, =0x150
1111 bic r0, r1, #0xFF000000
1112 bic r0, r0, #0x00FF0000
1119 ldr r0, =0x1e6e03d0 @ check Read Data Eye Training Pass Window
1121 ldr r2, =0x90
1122 bic r0, r1, #0x0000FF00
1131 ldr r0, =0x1e784000
1132 mov r1, #0x31 @ '1'
1136 ldr r0, =0x1e6e000c
1137 ldr r1, =0x00000040
1141 ldr r0, =0x1e6e0028
1142 ldr r1, =0x00000025
1145 ldr r0, =0x1e6e0028
1146 ldr r1, =0x00000027
1149 ldr r0, =0x1e6e0028
1150 ldr r1, =0x00000023
1153 ldr r0, =0x1e6e0028
1154 ldr r1, =0x00000021
1158 ldr r0, =0x1e6e0028
1159 ldr r1, =0x00000005
1162 ldr r0, =0x1e6e0028
1163 ldr r1, =0x00000007
1166 ldr r0, =0x1e6e0028
1167 ldr r1, =0x00000003
1170 ldr r0, =0x1e6e0028
1171 ldr r1, =0x00000011
1174 ldr r0, =0x1e6e000c
1175 ldr r1, =0x00005C41
1178 ldr r0, =0x1e6e0034
1179 ldr r2, =0x70000000
1185 ldr r0, =0x1e6e000c
1187 ldr r1, =0x42AA2F81
1189 ldr r1, =0x42AA5C81
1193 ldr r0, =0x1e6e0034
1194 ldr r1, =0x0001AF93
1197 ldr r0, =0x1e6e0120 @ VGA Compatible Mode
1211 ldr r0, =0x1e784000
1212 mov r1, #0x34 @ '4'
1214 mov r1, #0x0D @ '\r'
1216 mov r1, #0x0A @ '\n'
1226 ldr r0, =0x1e6e0004
1228 ldr r1, =0x00002313 @ Init to 8GB
1230 ldr r1, =0x00000313 @ Init to 8GB
1234 ldr r0, =0x1e6e0010
1238 ldr r0, =0x1e6e0014
1242 ldr r0, =0x1e6e0018
1247 ldr r0, =0x1e6e0020 @ MRS_4/6
1251 ldr r0, =0x1e6e0024 @ MRS_5
1255 ldr r0, =0x1e6e002c @ MRS_0/2
1257 mov r2, #0x1
1261 ldr r0, =0x1e6e0030 @ MRS_1/3
1266 ldr r0, =0x1e6e0200
1267 ldr r1, =0x42492AAE
1270 ldr r0, =0x1e6e0204
1271 ldr r1, =0x09002800
1274 ldr r0, =0x1e6e020c
1275 ldr r1, =0x55E00B0B
1278 ldr r0, =0x1e6e0210
1279 ldr r1, =0x20000000
1282 ldr r0, =0x1e6e0214
1286 ldr r0, =0x1e6e02e0
1290 ldr r0, =0x1e6e02e4
1294 ldr r0, =0x1e6e02e8
1298 ldr r0, =0x1e6e02ec
1302 ldr r0, =0x1e6e02f0
1306 ldr r0, =0x1e6e02f4
1310 ldr r0, =0x1e6e02f8
1314 ldr r0, =0x1e6e0290
1315 ldr r1, =0x00100008
1318 ldr r0, =0x1e6e02c4
1319 ldr r1, =0x3C183C3C
1322 ldr r0, =0x1e6e02c8
1323 ldr r1, =0x00631E0E
1326 ldr r0, =0x1e6e0034
1327 ldr r1, =0x0001A991
1331 ldr r0, =0x1e784000
1332 mov r1, #0x30 @ '0'
1339 Set Ron_pu = 0, Ron_pd = trained value
1342 ldr r0, =0x1e6e02c0
1343 ldr r1, =0x00001806
1345 ldr r0, =0x1e6e02cc
1346 ldr r1, =0x00005050
1348 ldr r0, =0x1e6e0120
1349 mov r1, #0x04
1351 ldr r0, =0x1e6e0060 @ Fire DDRPHY Init
1352 mov r1, #0x05
1358 ldr r0, =0x1e6e0300 @ read calibrated Ron_pd
1360 bic r3, r3, #0xFFFFFF0F
1361 ldr r0, =0x1e6e0240
1363 bic r1, r1, #0xFF000000
1372 orr r1, r1, #0x02
1375 ldr r0, =0x1e6e0060 @ Reset PHY
1376 mov r1, #0x00
1388 ldr r0, =0x1e720000 @ retry count
1389 mov r1, #0x5
1392 mov r7, #0x0
1393 mov r8, #0x0
1394 mov r10, #0x3F
1396 ldr r0, =0x1e720000
1398 subs r1, r1, #0x01
1402 ldr r0, =0x1e6e0120
1403 ldr r1, =0x00000001
1407 ldr r0, =0x1e784000
1408 mov r1, #0x61 @ 'a'
1412 ldr r0, =0x1e6e02c0
1413 ldr r1, =0x00001C06
1417 ldr r0, =0x1e6e0060
1418 ldr r1, =0x00000000
1421 add r10, r10, #0x01
1422 cmp r10, #0x80
1425 ldr r0, =0x1e6e02cc
1429 ldr r0, =0x1e6e0060
1430 ldr r1, =0x00000005
1439 ldr r0, =0x1e6e03d0 @ read eye pass window
1441 ldr r0, =0x1e720000
1444 cmp r9, #0x01
1446 add r8, r8, #0x01
1447 ldr r0, =0x1e6e03d0 @ read eye pass window
1450 and r1, r1, #0xFF @ r1 = DQL
1459 cmp r8, #0x0
1461 cmp r10, #0x80
1468 ldr r0, =0x1e6e02cc
1471 ldr r0, =0x1e720010
1485 ldr r0, =0x1e720000 @ retry count
1486 mov r1, #0x5
1489 mov r6, #0xFF
1490 mov r7, #0x0
1491 mov r8, #0x0
1492 mov r10, #0x0
1494 ldr r0, =0x1e720000
1496 subs r1, r1, #0x01
1500 ldr r0, =0x1e6e0120
1501 ldr r1, =0x00000002
1505 ldr r0, =0x1e784000
1506 mov r1, #0x62 @ 'b'
1511 ldr r0, =0x1e6e0060
1512 ldr r1, =0x00000000
1515 add r10, r10, #0x01
1516 cmp r10, #0x40
1519 ldr r0, =0x1e6e02c0
1520 mov r1, #0x06
1524 ldr r0, =0x1e6e0060
1525 ldr r1, =0x00000005
1534 cmp r9, #0x01
1536 add r8, r8, #0x01
1544 cmp r8, #0x0
1546 cmp r10, #0x40
1551 ldr r0, =0x1e6e0060
1552 ldr r1, =0x00000000
1557 ldr r0, =0x1e6e02c0
1559 add r1, r1, #0x01
1562 orr r1, r1, #0x06
1564 ldr r0, =0x1e720014
1570 ldr r0, =0x1e784000
1571 mov r1, #0x63 @ 'c'
1575 ldr r0, =0x1e6e0120
1576 ldr r1, =0x00000003
1579 ldr r0, =0x1e6e0060 @ Fire DDRPHY Init
1580 ldr r1, =0x00000005
1589 ldr r0, =0x1e6e03a0 @ check Gate Training Pass Window
1591 ldr r2, =0x150
1592 bic r0, r1, #0xFF000000
1593 bic r0, r0, #0x00FF0000
1600 ldr r0, =0x1e6e03d0 @ check Read Data Eye Training Pass Window
1602 ldr r2, =0x90
1603 bic r0, r1, #0x0000FF00
1613 ldr r0, =0x1e784000
1614 mov r1, #0x31 @ '1'
1618 ldr r0, =0x1e6e000c
1620 ldr r1, =0x42AA2F81
1622 ldr r1, =0x42AA5C81
1626 ldr r0, =0x1e6e0034
1627 ldr r1, =0x0001AF93
1630 ldr r0, =0x1e6e0120 @ VGA Compatible Mode
1649 ldr r2, =0x000493E0 @ Set Timer3 Reload = 300 ms
1651 ldr r3, =0x1e6e0060
1656 tst r1, #0x01
1660 ldr r0, =0x1e6e0300
1661 ldr r2, =0x000A0000
1667 ldr r0, =0x1e6e0060 @ Reset PHY
1668 mov r1, #0x00
1672 ldr r0, =0x1e784000
1673 mov r1, #0x2E @ '.'
1679 ldr r2, =0x0000000A @ Set Timer3 Reload = 10 us
1687 ldr r0, =0x1e6e0060 @ Fire PHY Init
1688 mov r1, #0x05
1694 ldr r0, =0x1e6e0060
1695 mov r1, #0x06
1698 ldr r0, =0x1e6e0120
1700 cmp r1, #0
1716 ldr r0, =0x1e6e000c
1717 ldr r1, =0x00005C01
1719 ldr r0, =0x1e6e0074
1720 ldr r1, =0x0000FFFF @ test size = 64KB
1722 ldr r0, =0x1e6e007c
1723 ldr r1, =0xFF00FF00
1727 ldr r0, =0x1e6e0070
1728 ldr r1, =0x00000000
1730 ldr r1, =0x00000085
1732 ldr r3, =0x3000
1733 ldr r11, =0x50000
1741 ldr r0, =0x1e6e0070 @ read fail bit status
1742 ldr r3, =0x2000
1748 mov r1, #0x00 @ initialize loop index, r1 is loop index
1750 ldr r0, =0x1e6e0070
1751 ldr r2, =0x00000000
1754 orr r2, r2, #0xC1 @ test command = 0xC1 | (datagen << 3)
1756 ldr r3, =0x3000
1757 ldr r11, =0x20000
1765 ldr r0, =0x1e6e0070 @ read fail bit status
1766 ldr r3, =0x2000
1772 cmp r1, #0x04 @ test 4 modes
1775 ldr r0, =0x1e6e0070
1776 ldr r1, =0x00000000
1778 mov r9, #0x1
1782 ldr r0, =0x1e6e0070
1783 ldr r1, =0x00000000
1785 mov r9, #0x0 @ CBRTest() return(0)
1788 ldr r0, =0x1e6e000c
1789 ldr r1, =0x00000000
1791 ldr r0, =0x1e6e0120
1804 1Gb : 0x80000000 ~ 0x87FFFFFF
1805 2Gb : 0x80000000 ~ 0x8FFFFFFF
1806 4Gb : 0x80000000 ~ 0x9FFFFFFF
1807 8Gb : 0x80000000 ~ 0xBFFFFFFF
1809 ldr r0, =0x1e6e0004
1811 bic r6, r6, #0x00000003 @ record MCR04
1815 ldr r0, =0xA0100000
1816 ldr r1, =0x41424344
1818 ldr r0, =0x90100000
1819 ldr r1, =0x35363738
1821 ldr r0, =0x88100000
1822 ldr r1, =0x292A2B2C
1824 ldr r0, =0x80100000
1825 ldr r1, =0x1D1E1F10
1827 ldr r0, =0xA0100000
1828 ldr r1, =0x41424344
1831 orreq r6, r6, #0x03
1833 mov r3, #0x38 @ '8'
1835 ldr r0, =0x90100000
1836 ldr r1, =0x35363738
1839 orreq r6, r6, #0x02
1841 mov r3, #0x34 @ '4'
1843 ldr r0, =0x88100000
1844 ldr r1, =0x292A2B2C
1847 orreq r6, r6, #0x01
1849 mov r3, #0x32 @ '2'
1851 mov r3, #0x31 @ '1'
1854 ldr r0, =0x1e6e0004
1856 ldr r0, =0x1e6e0014
1858 bic r1, r1, #0x000000FF
1859 and r7, r7, #0xFF
1864 ldr r0, =0x1e6e0004
1870 ldr r0, =0x1e6e0088
1875 ldr r0, =0x1e784000
1876 mov r1, #0x2D @ '-'
1879 mov r1, #0x47 @ 'G'
1881 mov r1, #0x62 @ 'b'
1883 mov r1, #0x2D @ '-'
1888 ldr r0, =0x1e6e0004
1893 ldr r3, =0x00080000
1903 ldr r0, =0x1e6e001c
1904 ldr r1, =0x00000008
1906 ldr r0, =0x1e6e0038
1907 ldr r1, =0xFFFFFF00
1914 ldr r0, =0x1e6e0074
1915 ldr r1, =0x0000FFFF @ test size = 64KB
1917 ldr r0, =0x1e6e007c
1918 ldr r1, =0xFF00FF00
1922 mov r1, #0x00 @ initialize loop index, r1 is loop index
1924 ldr r0, =0x1e6e0070
1925 ldr r2, =0x00000000
1928 orr r2, r2, #0xC1 @ test command = 0xC1 | (datagen << 3)
1930 ldr r3, =0x3000
1931 ldr r11, =0x20000
1939 ldr r0, =0x1e6e0070 @ read fail bit status
1940 ldr r3, =0x2000
1946 cmp r1, #0x01 @ test 1 modes
1949 ldr r0, =0x1e6e0070
1950 ldr r1, =0x00000000
1956 ldr r0, =0x1e784000
1957 mov r1, #0x46 @ 'F'
1959 mov r1, #0x61 @ 'a'
1961 mov r1, #0x69 @ 'i'
1963 mov r1, #0x6C @ 'l'
1965 mov r1, #0x0D @ '\r'
1967 mov r1, #0x0A @ '\n'
1969 ldr r0, =0x1e784014
1972 tst r1, #0x40
1979 ldr r0, =0x1e6e2040
1981 orr r1, r1, #0x41
1985 ldr r0, =0x1e784000
1986 mov r1, #0x44 @ 'D'
1988 mov r1, #0x6F @ 'o'
1990 mov r1, #0x6E @ 'n'
1992 mov r1, #0x65 @ 'e'
1994 mov r1, #0x0D @ '\r'
1996 mov r1, #0x0A @ '\n'
2001 ldr r0, =0x1e6e202c
2003 bic r1, r1, #0x40
2008 ldr r0, =0x1e784014
2011 tst r1, #0x40
2014 ldr r0, =0x1e784000
2015 mov r1, #0x52 @ 'R'
2017 mov r1, #0x65 @ 'e'
2019 mov r1, #0x61 @ 'a'
2021 mov r1, #0x64 @ 'd'
2023 mov r1, #0x20 @ ' '
2025 mov r1, #0x6D @ 'm'
2027 mov r1, #0x61 @ 'a'
2029 mov r1, #0x72 @ 'r'
2031 mov r1, #0x67 @ 'g'
2033 mov r1, #0x69 @ 'i'
2035 mov r1, #0x6E @ 'n'
2037 mov r1, #0x2D @ '-'
2039 mov r1, #0x44 @ 'D'
2041 mov r1, #0x4C @ 'L'
2043 mov r1, #0x3A @ ':'
2046 ldr r0, =0x1e784014
2049 tst r1, #0x40
2052 ldr r7, =0x000001FE @ divide by 510
2054 mov r9, #0 @ record violation
2055 ldr r0, =0x1e6e0004
2057 tst r1, #0x10 @ bit[4]=1 => DDR4
2058 movne r10, #0x9A @ DDR4 min = 0x99 (0.30)
2059 moveq r10, #0xB3 @ DDR3 min = 0xB3 (0.35)
2061 ldr r0, =0x1e6e03d0
2063 and r2, r2, #0xFF
2066 ldr r0, =0x1e784000
2067 mov r1, #0x30 @ '0'
2069 mov r1, #0x2E @ '.'
2071 mov r3, #0x4 @ print 4 digits
2076 mov r6, #0x0
2079 add r6, r6, #0x1
2085 mov r1, #0x30 @ '0'
2089 add r1, r6, #0x30 @ print n
2094 cmp r2, #0x0
2099 mov r1, #0x2F @ '/'
2101 mov r1, #0x44 @ 'D'
2103 mov r1, #0x48 @ 'H'
2105 mov r1, #0x3A @ ':'
2108 ldr r0, =0x1e784014
2111 tst r1, #0x40
2114 ldr r0, =0x1e6e03d0
2117 and r2, r2, #0xFF
2120 ldr r0, =0x1e784000
2121 mov r1, #0x30 @ '0'
2123 mov r1, #0x2E @ '.'
2125 mov r3, #0x4 @ print 4 digits
2130 mov r6, #0x0
2133 add r6, r6, #0x1
2139 mov r1, #0x30 @ '0'
2143 add r1, r6, #0x30 @ print n
2148 cmp r2, #0x0
2153 mov r1, #0x20 @ ' '
2155 mov r1, #0x43 @ 'C'
2157 mov r1, #0x4B @ 'K'
2160 ldr r0, =0x1e6e0004
2162 tst r1, #0x10 @ bit[4]=1 => DDR4
2163 movne r10, #0x30 @ DDR4 min = 0.30
2164 moveq r10, #0x35 @ DDR4 min = 0.35
2166 ldr r0, =0x1e784014
2169 tst r1, #0x40
2172 ldr r0, =0x1e784000
2173 mov r1, #0x20 @ ' '
2175 mov r1, #0x28 @ '('
2177 mov r1, #0x6D @ 'm'
2179 mov r1, #0x69 @ 'i'
2181 mov r1, #0x6E @ 'n'
2183 mov r1, #0x3A @ ':'
2185 mov r1, #0x30 @ '0'
2187 mov r1, #0x2E @ '.'
2189 mov r1, #0x33 @ '3'
2192 mov r1, #0x29 @ ')'
2195 cmp r9, #0
2197 mov r1, #0x20 @ ' '
2199 ldr r0, =0x1e784014
2202 tst r1, #0x40
2205 ldr r0, =0x1e784000
2206 mov r1, #0x57 @ 'W'
2208 mov r1, #0x61 @ 'a'
2210 mov r1, #0x72 @ 'r'
2212 mov r1, #0x6E @ 'n'
2214 mov r1, #0x69 @ 'i'
2216 mov r1, #0x6E @ 'n'
2218 mov r1, #0x67 @ 'g'
2220 mov r1, #0x3A @ ':'
2222 mov r1, #0x20 @ ' '
2224 mov r1, #0x4D @ 'M'
2226 mov r1, #0x61 @ 'a'
2228 mov r1, #0x72 @ 'r'
2230 mov r1, #0x67 @ 'g'
2232 mov r1, #0x69 @ 'i'
2234 mov r1, #0x6E @ 'n'
2236 ldr r0, =0x1e784014
2239 tst r1, #0x40
2241 ldr r0, =0x1e784000
2242 mov r1, #0x20 @ ' '
2244 mov r1, #0x74 @ 't'
2246 mov r1, #0x6F @ 'o'
2248 mov r1, #0x6F @ 'o'
2250 mov r1, #0x20 @ ' '
2252 mov r1, #0x73 @ 's'
2254 mov r1, #0x6D @ 'm'
2256 mov r1, #0x61 @ 'a'
2258 mov r1, #0x6C @ 'l'
2260 mov r1, #0x6C @ 'l'
2264 mov r1, #0x0D @ '\r'
2266 mov r1, #0x0A @ '\n'
2272 ldr r0, =0x1e6e0004
2273 ldr r2, =0x00000880 @ add cache range control, 2016.09.02
2278 ldr r0, =0x1e6e0054
2282 ldr r0, =0x1e6e007C
2283 ldr r1, =0x00000000
2285 ldr r0, =0x1e6e0074
2288 ldr r0, =0x1e6e0070
2289 ldr r1, =0x00000221
2292 ldr r2, =0x00001000
2298 ldr r1, =0x00000000
2301 ldr r0, =0x1e6e0050
2302 ldr r1, =0x80000000
2305 ldr r0, =0x1e6e0050
2306 ldr r1, =0x00000000
2309 ldr r0, =0x1e6e0070
2310 ldr r1, =0x00000400 @ Enable ECC auto-scrubbing
2318 mov r2, #0x0
2319 mov r6, #0x0
2320 mov r7, #0x0
2326 ldr r0, =0x1e620090
2328 ldr r0, =0x1e620080
2329 mov r1, #0x0
2332 ldr r0, =0x1e620010 @ set to fast read mode
2333 ldr r1, =0x000B0041
2336 ldr r6, =0x00F7E6D0 @ Init spiclk loop
2337 mov r8, #0x0 @ Init delay record
2340 mov r6, r6, lsr #0x4
2341 cmp r6, #0x0
2344 mov r7, #0x0 @ Init delay loop
2348 mov r2, #0x8
2354 ldr r0, =0x1e620090
2356 ldr r0, =0x1e620080
2357 mov r1, #0x0
2362 mov r2, #0x0
2368 ldr r0, =0x1e620090
2370 ldr r0, =0x1e620080
2371 mov r1, #0x0
2380 add r7, r7, #0x1
2381 cmp r7, #0x6
2386 ldr r0, =0x1e620094
2388 ldr r0, =0x1e620010
2389 mov r1, #0x0
2397 ldr r0, =0x1e600000
2398 ldr r1, =0xAEED1A03
2401 ldr r0, =0x1e600080
2402 ldr r2, =0x100
2408 ldr r0, =0x1e6e200c
2410 ldr r2, =0xF9FFFFFF
2412 ldr r2, =0x10000000
2416 ldr r0, =0x1e6e2008 @ Set Video ECLK phase
2418 ldr r2, =0x0ffffff3
2422 … ldr r0, =0x1e6e2004 @ Enable JTAG Master, solve ARM stucked by JTAG issue
2424 bic r1, r1, #0x00400000
2431 ldr r0, =0x1e6e213c
2432 ldr r1, =0x00000585 @ Reset D2PLL
2435 ldr r0, =0x1e6e202c
2437 bic r1, r1, #0x10 @ Enable D2PLL
2438 ldr r2, =0x00200000 @ Set CRT = 40MHz
2442 ldr r2, =0x8E00A17C @ Set to 250MHz
2444 ldr r0, =0x1e6e2070 @ Check CLKIN = 25MHz
2447 tst r1, #0x01
2449 ldr r2, =0x8E00A177
2452 ldr r0, =0x1e6e201c
2454 ldr r0, =0x1e6e213c @ Enable D2PLL
2455 ldr r1, =0x00000580
2458 ldr r0, =0x1e6e204c
2460 bic r1, r1, #0xFF0000
2461 ldr r2, =0x00040000 @ Set divider ratio
2465 ldr r0, =0x1e6e2048 @ Set MAC interface delay timing = 1G
2466 ldr r1, =0x80082208 @ Select internal 125MHz
2468 ldr r0, =0x1e6e20b8 @ Set MAC interface delay timing = 100M
2470 ldr r0, =0x1e6e20bc @ Set MAC interface delay timing = 10M
2473 ldr r0, =0x1e6e2070 @ Set MAC AHB bus clock
2475 mov r2, #0x04 @ Default RMII, set MHCLK = HPLL/10
2476 tst r1, #0xC0
2477 movne r2, #0x02 @ if RGMII, set MHCLK = HPLL/6
2478 ldr r0, =0x1e6e2008
2480 bic r1, r1, #0x00070000
2484 ldr r0, =0x1e6e21dc @ Set MAC duty
2485 ldr r1, =0x00666400
2488 ldr r0, =0x1e6e2090 @ Enable MAC interface pull low
2490 bic r1, r1, #0x0000F000
2491 bic r1, r1, #0x20000000 @ Set USB portA as Device mode
2495 ldr r0, =0x1e782040
2497 ldr r0, =0xFFFFFFFF
2499 ldr r0, =0x1e6e008c
2501 ldr r0, =0x1e78203c
2502 ldr r1, =0x0000F000
2506 ldr r0, =0x1e6e0000 @ disable MMC password
2507 mov r1, #0x0
2511 ldr r0, =0x1e782038
2512 ldr r1, =0xEA