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/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dqcom,ebi2.txt24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
58 ranges = <0 0x0 0x1a800000 0x00800000>,
59 <1 0x0 0x1b000000 0x00800000>,
60 <2 0x0 0x1b800000 0x00800000>,
61 <3 0x0 0x1d000000 0x08000000>,
[all …]
H A Dbaikal,bt1-apb.yaml74 reg = <0x1f059000 0x1000>,
75 <0x1d000000 0x2040000>;
/openbmc/u-boot/configs/
H A Dbcm23550_w1d_defconfig4 CONFIG_SYS_TEXT_BASE=0x9f000000
26 CONFIG_FASTBOOT_BUF_ADDR=0x80000000
27 CONFIG_FASTBOOT_BUF_SIZE=0x1D000000
29 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
37 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
38 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
/openbmc/linux/arch/mips/cobalt/
H A Dbuttons.c13 .start = 0x1d000000,
14 .end = 0x1d000003,
35 return 0; in cobalt_add_buttons()
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl172.txt11 first address cell and it may accept values 0..N-1
88 Example for pl172 with nor flash on chip select 0 shown below.
92 reg = <0x40005000 0x1000>;
97 ranges = <0 0 0x1c000000 0x1000000
98 1 0 0x1d000000 0x1000000
99 2 0 0x1e000000 0x1000000
100 3 0 0x1f000000 0x1000000>;
107 mpmc,cs = <0>;
110 mpmc,write-enable-delay = <0>;
111 mpmc,output-enable-delay = <0>;
[all …]
/openbmc/u-boot/board/kmc/kzm9g/
H A Dkzm9g.c16 #define CS0BCR_D (0x06C00400)
17 #define CS4BCR_D (0x16c90400)
18 #define CS0WCR_D (0x55062C42)
19 #define CS4WCR_D (0x1e071dc3)
24 #define VCLKCR1_D (0x27)
31 #define PORT32CR (0xE6051020)
32 #define PORT33CR (0xE6051021)
33 #define PORT34CR (0xE6051022)
34 #define PORT35CR (0xE6051023)
42 while (timeout > 0) { in cmp_loop()
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dep8248e.dts26 #size-cells = <0>;
28 PowerPC,8248@0 {
30 reg = <0>;
35 timebase-frequency = <0>;
36 clock-frequency = <0>;
46 reg = <0xf0010100 0x40>;
48 ranges = <0 0 0xfc000000 0x04000000
49 1 0 0xfa000000 0x00008000>;
51 flash@0,3800000 {
53 reg = <0 0x3800000 0x800000>;
[all …]
/openbmc/linux/arch/arm/mach-versatile/
H A Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dintegratorcp.dts19 #size-cells = <0>;
21 cpu@0 {
30 reg = <0>;
35 operating-points = <50000 0
36 48000 0>;
51 #clock-cells = <0>;
58 #clock-cells = <0>;
67 #clock-cells = <0>;
74 #clock-cells = <0>;
80 pclk: pclk@0 {
[all …]
/openbmc/linux/drivers/dma/
H A Dfsl_raid.h47 #define FSL_RE_GFM_POLY 0x1d000000
50 #define FSL_RE_CFG1_CBSI 0x08000000
51 #define FSL_RE_CFG1_CBS0 0x00080000
56 #define FSL_RE_PQ_OPCODE 0x1B
57 #define FSL_RE_XOR_OPCODE 0x1A
58 #define FSL_RE_MOVE_OPCODE 0x8
60 #define FSL_RE_BLOCK_SIZE 0x3 /* 4096 bytes */
61 #define FSL_RE_CACHEABLE_IO 0x0
62 #define FSL_RE_BUFFER_OUTPUT 0x0
63 #define FSL_RE_INTR_ON_ERROR 0x1
[all …]
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi23 service_reserved: svcbuffer@0 {
25 reg = <0x0 0x80000000 0x0 0x2000000>;
26 alignment = <0x1000>;
33 #size-cells = <0>;
35 cpu0: cpu@0 {
37 reg = <0x0>;
44 reg = <0x100>;
51 reg = <0x200>;
58 reg = <0x300>;
71 reg = <0x0 0x1d000000 0 0x10000>,
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8660.dtsi18 #size-cells = <0>;
20 cpu@0 {
24 reg = <0>;
45 reg = <0x0 0x0>;
50 interrupts = <1 9 0x304>;
56 #clock-cells = <0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
83 io-channels = <&pm8058_xoadc 0x00 0x01>, /* Battery */
84 <&pm8058_xoadc 0x00 0x02>, /* DC in (charger) */
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc18xx.dtsi19 #define LPC_PIN(port, pin) (0x##port * 32 + pin)
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0x0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
53 #clock-cells = <0>;
54 clock-frequency = <0>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
[all …]
/openbmc/qemu/hw/arm/
H A Dintegratorcp.c58 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
59 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
86 if (offset >= 0x100 && offset < 0x200) { in integratorcm_read()
88 if (offset >= 0x180) in integratorcm_read()
89 return 0; in integratorcm_read()
93 case 0: /* CM_ID */ in integratorcm_read()
94 return 0x411a3001; in integratorcm_read()
96 return 0; in integratorcm_read()
102 return 0x00100000; in integratorcm_read()
104 if (s->cm_lock == 0xa05f) { in integratorcm_read()
[all …]
/openbmc/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]